1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40
41class Checkpoint;
42class EventManager;
43class ThreadContext;
44
45namespace SparcISA
46{
47class ISA
48{
49 private:
50
51 /* ASR Registers */
52 // uint64_t y; // Y (used in obsolete multiplication)
53 // uint8_t ccr; // Condition Code Register
54 uint8_t asi; // Address Space Identifier
55 uint64_t tick; // Hardware clock-tick counter

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195 }
196
197 int
198 flattenFloatIndex(int reg)
199 {
200 return reg;
201 }
202
203 ISA()
204 {
205 tickCompare = NULL;
206 sTickCompare = NULL;
207 hSTickCompare = NULL;
208
209 clear();
210 }
211};
212}
213
214#endif