isa.cc (9375:ecfd5607d5e9) isa.cc (9377:6f294e7a93d1)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/sparc/asi.hh"
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/decoder.hh"
32#include "arch/sparc/isa.hh"
33#include "base/bitfield.hh"
34#include "base/trace.hh"
35#include "cpu/base.hh"
36#include "cpu/thread_context.hh"
37#include "debug/MiscRegs.hh"
38#include "debug/Timer.hh"
39

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545
546void
547ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
548{
549 MiscReg new_val = val;
550
551 switch (miscReg) {
552 case MISCREG_ASI:
33#include "arch/sparc/isa.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38#include "debug/MiscRegs.hh"
39#include "debug/Timer.hh"
40

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546
547void
548ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
549{
550 MiscReg new_val = val;
551
552 switch (miscReg) {
553 case MISCREG_ASI:
553 tc->getDecodePtr()->setContext(val);
554 tc->getDecoderPtr()->setContext(val);
554 break;
555 case MISCREG_STICK:
556 case MISCREG_TICK:
557 // stick and tick are same thing on niagra
558 // use stick for offset and tick for holding intrrupt bit
559 stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
560 tick = mbits(val,63,63);
561 DPRINTF(Timer, "Writing TICK=%#X\n", val);

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556 case MISCREG_STICK:
557 case MISCREG_TICK:
558 // stick and tick are same thing on niagra
559 // use stick for offset and tick for holding intrrupt bit
560 stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
561 tick = mbits(val,63,63);
562 DPRINTF(Timer, "Writing TICK=%#X\n", val);

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