isa.cc (8232:b28d06a175be) isa.cc (8747:017e5bbbb4e2)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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131 cpu_mondo_tail = 0;
132 dev_mondo_head = 0;
133 dev_mondo_tail = 0;
134 res_error_head = 0;
135 res_error_tail = 0;
136 nres_error_head = 0;
137 nres_error_tail = 0;
138
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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131 cpu_mondo_tail = 0;
132 dev_mondo_head = 0;
133 dev_mondo_tail = 0;
134 res_error_head = 0;
135 res_error_tail = 0;
136 nres_error_head = 0;
137 nres_error_tail = 0;
138
139#if FULL_SYSTEM
140 // If one of these events is active, it's not obvious to me how to get
141 // rid of it cleanly. For now we'll just assert that they're not.
142 if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
143 panic("Tick comparison event active when clearing the ISA object.\n");
139 // If one of these events is active, it's not obvious to me how to get
140 // rid of it cleanly. For now we'll just assert that they're not.
141 if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
142 panic("Tick comparison event active when clearing the ISA object.\n");
144#endif
145}
146
147MiscReg
148ISA::readMiscRegNoEffect(int miscReg)
149{
150
151 // The three miscRegs are moved up from the switch statement
152 // due to more frequent calls.

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341 case MISCREG_QUEUE_CPU_MONDO_HEAD:
342 case MISCREG_QUEUE_CPU_MONDO_TAIL:
343 case MISCREG_QUEUE_DEV_MONDO_HEAD:
344 case MISCREG_QUEUE_DEV_MONDO_TAIL:
345 case MISCREG_QUEUE_RES_ERROR_HEAD:
346 case MISCREG_QUEUE_RES_ERROR_TAIL:
347 case MISCREG_QUEUE_NRES_ERROR_HEAD:
348 case MISCREG_QUEUE_NRES_ERROR_TAIL:
143}
144
145MiscReg
146ISA::readMiscRegNoEffect(int miscReg)
147{
148
149 // The three miscRegs are moved up from the switch statement
150 // due to more frequent calls.

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339 case MISCREG_QUEUE_CPU_MONDO_HEAD:
340 case MISCREG_QUEUE_CPU_MONDO_TAIL:
341 case MISCREG_QUEUE_DEV_MONDO_HEAD:
342 case MISCREG_QUEUE_DEV_MONDO_TAIL:
343 case MISCREG_QUEUE_RES_ERROR_HEAD:
344 case MISCREG_QUEUE_RES_ERROR_TAIL:
345 case MISCREG_QUEUE_NRES_ERROR_HEAD:
346 case MISCREG_QUEUE_NRES_ERROR_TAIL:
349#if FULL_SYSTEM
350 case MISCREG_HPSTATE:
351 return readFSReg(miscReg, tc);
347 case MISCREG_HPSTATE:
348 return readFSReg(miscReg, tc);
352#else
353 case MISCREG_HPSTATE:
354 // HPSTATE is special because because sometimes in privilege
355 // checks for instructions it will read HPSTATE to make sure
356 // the priv. level is ok So, we'll just have to tell it it
357 // isn't, instead of panicing.
358 return 0;
359
360 panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
361#endif
362
363 }
364 return readMiscRegNoEffect(miscReg);
365}
366
367void
368ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
369{
370 switch (miscReg) {

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564 case MISCREG_PCR:
565 // Set up performance counting based on pcr value
566 break;
567 case MISCREG_PSTATE:
568 pstate = val & PSTATE_MASK;
569 return;
570 case MISCREG_TL:
571 tl = val;
349 }
350 return readMiscRegNoEffect(miscReg);
351}
352
353void
354ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
355{
356 switch (miscReg) {

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550 case MISCREG_PCR:
551 // Set up performance counting based on pcr value
552 break;
553 case MISCREG_PSTATE:
554 pstate = val & PSTATE_MASK;
555 return;
556 case MISCREG_TL:
557 tl = val;
572#if FULL_SYSTEM
573 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
574 tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
575 else
576 tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
558 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
559 tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
560 else
561 tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
577#endif
578 return;
579 case MISCREG_CWP:
580 new_val = val >= NWindows ? NWindows - 1 : val;
581 if (val >= NWindows)
582 new_val = NWindows - 1;
583
584 installWindow(new_val, CurrentWindowOffset);
585 installWindow(new_val - 1, NextWindowOffset);

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605 case MISCREG_QUEUE_CPU_MONDO_HEAD:
606 case MISCREG_QUEUE_CPU_MONDO_TAIL:
607 case MISCREG_QUEUE_DEV_MONDO_HEAD:
608 case MISCREG_QUEUE_DEV_MONDO_TAIL:
609 case MISCREG_QUEUE_RES_ERROR_HEAD:
610 case MISCREG_QUEUE_RES_ERROR_TAIL:
611 case MISCREG_QUEUE_NRES_ERROR_HEAD:
612 case MISCREG_QUEUE_NRES_ERROR_TAIL:
562 return;
563 case MISCREG_CWP:
564 new_val = val >= NWindows ? NWindows - 1 : val;
565 if (val >= NWindows)
566 new_val = NWindows - 1;
567
568 installWindow(new_val, CurrentWindowOffset);
569 installWindow(new_val - 1, NextWindowOffset);

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589 case MISCREG_QUEUE_CPU_MONDO_HEAD:
590 case MISCREG_QUEUE_CPU_MONDO_TAIL:
591 case MISCREG_QUEUE_DEV_MONDO_HEAD:
592 case MISCREG_QUEUE_DEV_MONDO_TAIL:
593 case MISCREG_QUEUE_RES_ERROR_HEAD:
594 case MISCREG_QUEUE_RES_ERROR_TAIL:
595 case MISCREG_QUEUE_NRES_ERROR_HEAD:
596 case MISCREG_QUEUE_NRES_ERROR_TAIL:
613#if FULL_SYSTEM
614 case MISCREG_HPSTATE:
615 setFSReg(miscReg, val, tc);
616 return;
597 case MISCREG_HPSTATE:
598 setFSReg(miscReg, val, tc);
599 return;
617#else
618 case MISCREG_HPSTATE:
619 // HPSTATE is special because normal trap processing saves HPSTATE when
620 // it goes into a trap, and restores it when it returns.
621 return;
622 panic("Accessing Fullsystem register %d to %#x in SE mode\n",
623 miscReg, val);
624#endif
625 }
626 setMiscRegNoEffect(miscReg, new_val);
627}
628
629void
630ISA::serialize(EventManager *em, std::ostream &os)
631{
632 SERIALIZE_SCALAR(asi);

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662 SERIALIZE_SCALAR(cpu_mondo_head);
663 SERIALIZE_SCALAR(cpu_mondo_tail);
664 SERIALIZE_SCALAR(dev_mondo_head);
665 SERIALIZE_SCALAR(dev_mondo_tail);
666 SERIALIZE_SCALAR(res_error_head);
667 SERIALIZE_SCALAR(res_error_tail);
668 SERIALIZE_SCALAR(nres_error_head);
669 SERIALIZE_SCALAR(nres_error_tail);
600 }
601 setMiscRegNoEffect(miscReg, new_val);
602}
603
604void
605ISA::serialize(EventManager *em, std::ostream &os)
606{
607 SERIALIZE_SCALAR(asi);

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637 SERIALIZE_SCALAR(cpu_mondo_head);
638 SERIALIZE_SCALAR(cpu_mondo_tail);
639 SERIALIZE_SCALAR(dev_mondo_head);
640 SERIALIZE_SCALAR(dev_mondo_tail);
641 SERIALIZE_SCALAR(res_error_head);
642 SERIALIZE_SCALAR(res_error_tail);
643 SERIALIZE_SCALAR(nres_error_head);
644 SERIALIZE_SCALAR(nres_error_tail);
670#if FULL_SYSTEM
671 Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
672 ThreadContext *tc = NULL;
673 BaseCPU *cpu = NULL;
674 int tc_num = 0;
675 bool tick_intr_sched = true;
676
677 if (tickCompare)
678 tc = tickCompare->getTC();

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696 hstick_cmp = hSTickCompare->when();
697
698 SERIALIZE_OBJPTR(cpu);
699 SERIALIZE_SCALAR(tc_num);
700 SERIALIZE_SCALAR(tick_cmp);
701 SERIALIZE_SCALAR(stick_cmp);
702 SERIALIZE_SCALAR(hstick_cmp);
703 }
645 Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
646 ThreadContext *tc = NULL;
647 BaseCPU *cpu = NULL;
648 int tc_num = 0;
649 bool tick_intr_sched = true;
650
651 if (tickCompare)
652 tc = tickCompare->getTC();

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670 hstick_cmp = hSTickCompare->when();
671
672 SERIALIZE_OBJPTR(cpu);
673 SERIALIZE_SCALAR(tc_num);
674 SERIALIZE_SCALAR(tick_cmp);
675 SERIALIZE_SCALAR(stick_cmp);
676 SERIALIZE_SCALAR(hstick_cmp);
677 }
704#endif
705}
706
707void
708ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
709{
710 UNSERIALIZE_SCALAR(asi);
711 UNSERIALIZE_SCALAR(tick);
712 UNSERIALIZE_SCALAR(fprs);

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742 UNSERIALIZE_SCALAR(cpu_mondo_tail);
743 UNSERIALIZE_SCALAR(dev_mondo_head);
744 UNSERIALIZE_SCALAR(dev_mondo_tail);
745 UNSERIALIZE_SCALAR(res_error_head);
746 UNSERIALIZE_SCALAR(res_error_tail);
747 UNSERIALIZE_SCALAR(nres_error_head);
748 UNSERIALIZE_SCALAR(nres_error_tail);
749
678}
679
680void
681ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
682{
683 UNSERIALIZE_SCALAR(asi);
684 UNSERIALIZE_SCALAR(tick);
685 UNSERIALIZE_SCALAR(fprs);

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715 UNSERIALIZE_SCALAR(cpu_mondo_tail);
716 UNSERIALIZE_SCALAR(dev_mondo_head);
717 UNSERIALIZE_SCALAR(dev_mondo_tail);
718 UNSERIALIZE_SCALAR(res_error_head);
719 UNSERIALIZE_SCALAR(res_error_tail);
720 UNSERIALIZE_SCALAR(nres_error_head);
721 UNSERIALIZE_SCALAR(nres_error_tail);
722
750#if FULL_SYSTEM
751 Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
752 ThreadContext *tc = NULL;
753 BaseCPU *cpu = NULL;
754 int tc_num;
755 bool tick_intr_sched;
756 UNSERIALIZE_SCALAR(tick_intr_sched);
757 if (tick_intr_sched) {
758 UNSERIALIZE_OBJPTR(cpu);

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773 }
774 if (hstick_cmp) {
775 hSTickCompare = new HSTickCompareEvent(this, tc);
776 em->schedule(hSTickCompare, hstick_cmp);
777 }
778 }
779 }
780
723 Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
724 ThreadContext *tc = NULL;
725 BaseCPU *cpu = NULL;
726 int tc_num;
727 bool tick_intr_sched;
728 UNSERIALIZE_SCALAR(tick_intr_sched);
729 if (tick_intr_sched) {
730 UNSERIALIZE_OBJPTR(cpu);

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745 }
746 if (hstick_cmp) {
747 hSTickCompare = new HSTickCompareEvent(this, tc);
748 em->schedule(hSTickCompare, hstick_cmp);
749 }
750 }
751 }
752
781 #endif
782}
783
784}
753}
754
755}