isa.cc (7703:90299d921559) isa.cc (7741:340b6f01d69b)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38
39namespace SparcISA
40{
41
42enum RegMask
43{
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36#include "cpu/base.hh"
37#include "cpu/thread_context.hh"
38
39namespace SparcISA
40{
41
42enum RegMask
43{
44 PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
44 PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
45};
46
47void
48ISA::reloadRegMap()
49{
50 installGlobals(gl, CurrentGlobalsOffset);
51 installWindow(cwp, CurrentWindowOffset);
52 // Microcode registers.

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80
81void
82ISA::clear()
83{
84 cwp = 0;
85 gl = 0;
86 reloadRegMap();
87
45};
46
47void
48ISA::reloadRegMap()
49{
50 installGlobals(gl, CurrentGlobalsOffset);
51 installWindow(cwp, CurrentWindowOffset);
52 // Microcode registers.

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80
81void
82ISA::clear()
83{
84 cwp = 0;
85 gl = 0;
86 reloadRegMap();
87
88 //y = 0;
89 //ccr = 0;
88 // y = 0;
89 // ccr = 0;
90 asi = 0;
91 tick = ULL(1) << 63;
92 fprs = 0;
93 gsr = 0;
94 softint = 0;
95 tick_cmpr = 0;
96 stick = 0;
97 stick_cmpr = 0;
98 memset(tpc, 0, sizeof(tpc));
99 memset(tnpc, 0, sizeof(tnpc));
100 memset(tstate, 0, sizeof(tstate));
101 memset(tt, 0, sizeof(tt));
102 tba = 0;
103 pstate = 0;
104 tl = 0;
105 pil = 0;
90 asi = 0;
91 tick = ULL(1) << 63;
92 fprs = 0;
93 gsr = 0;
94 softint = 0;
95 tick_cmpr = 0;
96 stick = 0;
97 stick_cmpr = 0;
98 memset(tpc, 0, sizeof(tpc));
99 memset(tnpc, 0, sizeof(tnpc));
100 memset(tstate, 0, sizeof(tstate));
101 memset(tt, 0, sizeof(tt));
102 tba = 0;
103 pstate = 0;
104 tl = 0;
105 pil = 0;
106 //cansave = 0;
107 //canrestore = 0;
108 //cleanwin = 0;
109 //otherwin = 0;
110 //wstate = 0;
111 //In a T1, bit 11 is apparently always 1
106 // cansave = 0;
107 // canrestore = 0;
108 // cleanwin = 0;
109 // otherwin = 0;
110 // wstate = 0;
111 // In a T1, bit 11 is apparently always 1
112 hpstate = (1 << 11);
113 memset(htstate, 0, sizeof(htstate));
114 hintp = 0;
115 htba = 0;
116 hstick_cmpr = 0;
112 hpstate = (1 << 11);
113 memset(htstate, 0, sizeof(htstate));
114 hintp = 0;
115 htba = 0;
116 hstick_cmpr = 0;
117 //This is set this way in Legion for some reason
117 // This is set this way in Legion for some reason
118 strandStatusReg = 0x50000;
119 fsr = 0;
120
121 priContext = 0;
122 secContext = 0;
123 partId = 0;
124 lsuCtrlReg = 0;
125

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170 bits((uint64_t)lsuCtrlReg,3,2) << 4 |
171 bits((uint64_t)partId,7,0) << 8 |
172 bits((uint64_t)tl,2,0) << 16 |
173 (uint64_t)priContext << 32 |
174 (uint64_t)secContext << 48;
175 }
176
177 switch (miscReg) {
118 strandStatusReg = 0x50000;
119 fsr = 0;
120
121 priContext = 0;
122 secContext = 0;
123 partId = 0;
124 lsuCtrlReg = 0;
125

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170 bits((uint64_t)lsuCtrlReg,3,2) << 4 |
171 bits((uint64_t)partId,7,0) << 8 |
172 bits((uint64_t)tl,2,0) << 16 |
173 (uint64_t)priContext << 32 |
174 (uint64_t)secContext << 48;
175 }
176
177 switch (miscReg) {
178 //case MISCREG_TLB_DATA:
178 // case MISCREG_TLB_DATA:
179 // [original contents see above]
179 // [original contents see above]
180 //case MISCREG_Y:
180 // case MISCREG_Y:
181 // return y;
181 // return y;
182 //case MISCREG_CCR:
182 // case MISCREG_CCR:
183 // return ccr;
184 case MISCREG_ASI:
185 return asi;
186 case MISCREG_FPRS:
187 return fprs;
188 case MISCREG_TICK:
189 return tick;
190 case MISCREG_PCR:

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216 case MISCREG_TBA:
217 return tba;
218 case MISCREG_PSTATE:
219 return pstate;
220 case MISCREG_TL:
221 return tl;
222 case MISCREG_PIL:
223 return pil;
183 // return ccr;
184 case MISCREG_ASI:
185 return asi;
186 case MISCREG_FPRS:
187 return fprs;
188 case MISCREG_TICK:
189 return tick;
190 case MISCREG_PCR:

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216 case MISCREG_TBA:
217 return tba;
218 case MISCREG_PSTATE:
219 return pstate;
220 case MISCREG_TL:
221 return tl;
222 case MISCREG_PIL:
223 return pil;
224 //CWP, GL moved
225 //case MISCREG_CWP:
226 // return cwp;
227 //case MISCREG_CANSAVE:
228 // return cansave;
229 //case MISCREG_CANRESTORE:
230 // return canrestore;
231 //case MISCREG_CLEANWIN:
232 // return cleanwin;
233 //case MISCREG_OTHERWIN:
234 // return otherwin;
235 //case MISCREG_WSTATE:
236 // return wstate;
237 //case MISCREG_GL:
238 // return gl;
224 // CWP, GL moved
225 // case MISCREG_CWP:
226 // return cwp;
227 // case MISCREG_CANSAVE:
228 // return cansave;
229 // case MISCREG_CANRESTORE:
230 // return canrestore;
231 // case MISCREG_CLEANWIN:
232 // return cleanwin;
233 // case MISCREG_OTHERWIN:
234 // return otherwin;
235 // case MISCREG_WSTATE:
236 // return wstate;
237 // case MISCREG_GL:
238 // return gl;
239
240 /** Hyper privileged registers */
241 case MISCREG_HPSTATE:
242 return hpstate;
243 case MISCREG_HTSTATE:
244 return htstate[tl-1];
245 case MISCREG_HINTP:
246 return hintp;

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344 case MISCREG_QUEUE_RES_ERROR_TAIL:
345 case MISCREG_QUEUE_NRES_ERROR_HEAD:
346 case MISCREG_QUEUE_NRES_ERROR_TAIL:
347#if FULL_SYSTEM
348 case MISCREG_HPSTATE:
349 return readFSReg(miscReg, tc);
350#else
351 case MISCREG_HPSTATE:
239
240 /** Hyper privileged registers */
241 case MISCREG_HPSTATE:
242 return hpstate;
243 case MISCREG_HTSTATE:
244 return htstate[tl-1];
245 case MISCREG_HINTP:
246 return hintp;

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344 case MISCREG_QUEUE_RES_ERROR_TAIL:
345 case MISCREG_QUEUE_NRES_ERROR_HEAD:
346 case MISCREG_QUEUE_NRES_ERROR_TAIL:
347#if FULL_SYSTEM
348 case MISCREG_HPSTATE:
349 return readFSReg(miscReg, tc);
350#else
351 case MISCREG_HPSTATE:
352 //HPSTATE is special because because sometimes in privilege
353 //checks for instructions it will read HPSTATE to make sure
354 //the priv. level is ok So, we'll just have to tell it it
355 //isn't, instead of panicing.
352 // HPSTATE is special because because sometimes in privilege
353 // checks for instructions it will read HPSTATE to make sure
354 // the priv. level is ok So, we'll just have to tell it it
355 // isn't, instead of panicing.
356 return 0;
357
358 panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
359#endif
360
361 }
362 return readMiscRegNoEffect(miscReg);
363}

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552 case MISCREG_TICK:
553 // stick and tick are same thing on niagra
554 // use stick for offset and tick for holding intrrupt bit
555 stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
556 tick = mbits(val,63,63);
557 DPRINTF(Timer, "Writing TICK=%#X\n", val);
558 break;
559 case MISCREG_FPRS:
356 return 0;
357
358 panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
359#endif
360
361 }
362 return readMiscRegNoEffect(miscReg);
363}

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552 case MISCREG_TICK:
553 // stick and tick are same thing on niagra
554 // use stick for offset and tick for holding intrrupt bit
555 stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
556 tick = mbits(val,63,63);
557 DPRINTF(Timer, "Writing TICK=%#X\n", val);
558 break;
559 case MISCREG_FPRS:
560 //Configure the fpu based on the fprs
560 // Configure the fpu based on the fprs
561 break;
562 case MISCREG_PCR:
561 break;
562 case MISCREG_PCR:
563 //Set up performance counting based on pcr value
563 // Set up performance counting based on pcr value
564 break;
565 case MISCREG_PSTATE:
566 pstate = val & PSTATE_MASK;
567 return;
568 case MISCREG_TL:
569 tl = val;
570#if FULL_SYSTEM
571 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))

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609 case MISCREG_QUEUE_NRES_ERROR_HEAD:
610 case MISCREG_QUEUE_NRES_ERROR_TAIL:
611#if FULL_SYSTEM
612 case MISCREG_HPSTATE:
613 setFSReg(miscReg, val, tc);
614 return;
615#else
616 case MISCREG_HPSTATE:
564 break;
565 case MISCREG_PSTATE:
566 pstate = val & PSTATE_MASK;
567 return;
568 case MISCREG_TL:
569 tl = val;
570#if FULL_SYSTEM
571 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))

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609 case MISCREG_QUEUE_NRES_ERROR_HEAD:
610 case MISCREG_QUEUE_NRES_ERROR_TAIL:
611#if FULL_SYSTEM
612 case MISCREG_HPSTATE:
613 setFSReg(miscReg, val, tc);
614 return;
615#else
616 case MISCREG_HPSTATE:
617 //HPSTATE is special because normal trap processing saves HPSTATE when
618 //it goes into a trap, and restores it when it returns.
617 // HPSTATE is special because normal trap processing saves HPSTATE when
618 // it goes into a trap, and restores it when it returns.
619 return;
620 panic("Accessing Fullsystem register %d to %#x in SE mode\n",
621 miscReg, val);
622#endif
623 }
624 setMiscRegNoEffect(miscReg, new_val);
625}
626

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620 panic("Accessing Fullsystem register %d to %#x in SE mode\n",
621 miscReg, val);
622#endif
623 }
624 setMiscRegNoEffect(miscReg, new_val);
625}
626

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