isa.cc (12620:fe5cdc0293dd) isa.cc (13583:f7482392b097)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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168 nres_error_tail = 0;
169
170 // If one of these events is active, it's not obvious to me how to get
171 // rid of it cleanly. For now we'll just assert that they're not.
172 if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
173 panic("Tick comparison event active when clearing the ISA object.\n");
174}
175
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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168 nres_error_tail = 0;
169
170 // If one of these events is active, it's not obvious to me how to get
171 // rid of it cleanly. For now we'll just assert that they're not.
172 if (tickCompare != NULL && sTickCompare != NULL && hSTickCompare != NULL)
173 panic("Tick comparison event active when clearing the ISA object.\n");
174}
175
176MiscReg
176RegVal
177ISA::readMiscRegNoEffect(int miscReg) const
178{
179
180 // The three miscRegs are moved up from the switch statement
181 // due to more frequent calls.
182
183 if (miscReg == MISCREG_GL)
184 return gl;

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243 return tstate[tl-1];
244 case MISCREG_TT:
245 return tt[tl-1];
246 case MISCREG_PRIVTICK:
247 panic("Priviliged access to tick registers not implemented\n");
248 case MISCREG_TBA:
249 return tba;
250 case MISCREG_PSTATE:
177ISA::readMiscRegNoEffect(int miscReg) const
178{
179
180 // The three miscRegs are moved up from the switch statement
181 // due to more frequent calls.
182
183 if (miscReg == MISCREG_GL)
184 return gl;

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243 return tstate[tl-1];
244 case MISCREG_TT:
245 return tt[tl-1];
246 case MISCREG_PRIVTICK:
247 panic("Priviliged access to tick registers not implemented\n");
248 case MISCREG_TBA:
249 return tba;
250 case MISCREG_PSTATE:
251 return (MiscReg)pstate;
251 return (RegVal)pstate;
252 case MISCREG_TL:
253 return tl;
254 case MISCREG_PIL:
255 return pil;
256 // CWP, GL moved
257 // case MISCREG_CWP:
258 // return cwp;
259 // case MISCREG_CANSAVE:

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266 // return otherwin;
267 // case MISCREG_WSTATE:
268 // return wstate;
269 // case MISCREG_GL:
270 // return gl;
271
272 /** Hyper privileged registers */
273 case MISCREG_HPSTATE:
252 case MISCREG_TL:
253 return tl;
254 case MISCREG_PIL:
255 return pil;
256 // CWP, GL moved
257 // case MISCREG_CWP:
258 // return cwp;
259 // case MISCREG_CANSAVE:

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266 // return otherwin;
267 // case MISCREG_WSTATE:
268 // return wstate;
269 // case MISCREG_GL:
270 // return gl;
271
272 /** Hyper privileged registers */
273 case MISCREG_HPSTATE:
274 return (MiscReg)hpstate;
274 return (RegVal)hpstate;
275 case MISCREG_HTSTATE:
276 return htstate[tl-1];
277 case MISCREG_HINTP:
278 return hintp;
279 case MISCREG_HTBA:
280 return htba;
281 case MISCREG_STRAND_STS_REG:
282 return strandStatusReg;

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329 return nres_error_head;
330 case MISCREG_QUEUE_NRES_ERROR_TAIL:
331 return nres_error_tail;
332 default:
333 panic("Miscellaneous register %d not implemented\n", miscReg);
334 }
335}
336
275 case MISCREG_HTSTATE:
276 return htstate[tl-1];
277 case MISCREG_HINTP:
278 return hintp;
279 case MISCREG_HTBA:
280 return htba;
281 case MISCREG_STRAND_STS_REG:
282 return strandStatusReg;

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329 return nres_error_head;
330 case MISCREG_QUEUE_NRES_ERROR_TAIL:
331 return nres_error_tail;
332 default:
333 panic("Miscellaneous register %d not implemented\n", miscReg);
334 }
335}
336
337MiscReg
337RegVal
338ISA::readMiscReg(int miscReg, ThreadContext * tc)
339{
340 switch (miscReg) {
341 // tick and stick are aliased to each other in niagra
342 // well store the tick data in stick and the interrupt bit in tick
343 case MISCREG_STICK:
344 case MISCREG_TICK:
345 case MISCREG_PRIVTICK:

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378 case MISCREG_QUEUE_NRES_ERROR_TAIL:
379 case MISCREG_HPSTATE:
380 return readFSReg(miscReg, tc);
381 }
382 return readMiscRegNoEffect(miscReg);
383}
384
385void
338ISA::readMiscReg(int miscReg, ThreadContext * tc)
339{
340 switch (miscReg) {
341 // tick and stick are aliased to each other in niagra
342 // well store the tick data in stick and the interrupt bit in tick
343 case MISCREG_STICK:
344 case MISCREG_TICK:
345 case MISCREG_PRIVTICK:

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378 case MISCREG_QUEUE_NRES_ERROR_TAIL:
379 case MISCREG_HPSTATE:
380 return readFSReg(miscReg, tc);
381 }
382 return readMiscRegNoEffect(miscReg);
383}
384
385void
386ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
386ISA::setMiscRegNoEffect(int miscReg, RegVal val)
387{
388 switch (miscReg) {
389// case MISCREG_Y:
390// y = val;
391// break;
392// case MISCREG_CCR:
393// ccr = val;
394// break;

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559 nres_error_tail = val;
560 break;
561 default:
562 panic("Miscellaneous register %d not implemented\n", miscReg);
563 }
564}
565
566void
387{
388 switch (miscReg) {
389// case MISCREG_Y:
390// y = val;
391// break;
392// case MISCREG_CCR:
393// ccr = val;
394// break;

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559 nres_error_tail = val;
560 break;
561 default:
562 panic("Miscellaneous register %d not implemented\n", miscReg);
563 }
564}
565
566void
567ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
567ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
568{
568{
569 MiscReg new_val = val;
569 RegVal new_val = val;
570
571 switch (miscReg) {
572 case MISCREG_ASI:
573 tc->getDecoderPtr()->setContext(val);
574 break;
575 case MISCREG_STICK:
576 case MISCREG_TICK:
577 // stick and tick are same thing on niagra

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571 switch (miscReg) {
572 case MISCREG_ASI:
573 tc->getDecoderPtr()->setContext(val);
574 break;
575 case MISCREG_STICK:
576 case MISCREG_TICK:
577 // stick and tick are same thing on niagra

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