interrupts.hh (4028:e936c7dc2d68) | interrupts.hh (4103:785279436bdd) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu |
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27 */ 28 29#ifndef __ARCH_SPARC_INTERRUPT_HH__ 30#define __ARCH_SPARC_INTERRUPT_HH__ 31 32#include "arch/sparc/faults.hh" | 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" |
36#include "arch/sparc/isa_traits.hh" |
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33#include "cpu/thread_context.hh" 34 35namespace SparcISA 36{ 37 | 37#include "cpu/thread_context.hh" 38 39namespace SparcISA 40{ 41 |
38enum interrupts_t { 39 trap_level_zero, 40 hstick_match, 41 interrupt_vector, 42 cpu_mondo, 43 dev_mondo, 44 resumable_error, 45 soft_interrupt, 46 num_interrupt_types 47}; 48 | |
49class Interrupts 50{ 51 52 private: 53 | 42class Interrupts 43{ 44 45 private: 46 |
54 bool interrupts[num_interrupt_types]; 55 int numPosted; | 47 uint64_t interrupts[NumInterruptTypes]; 48 uint64_t intStatus; |
56 57 public: 58 Interrupts() 59 { | 49 50 public: 51 Interrupts() 52 { |
60 for (int i = 0; i < num_interrupt_types; ++i) { 61 interrupts[i] = false; 62 } 63 numPosted = 0; | 53 clear_all(); |
64 } 65 | 54 } 55 |
66 void post(int int_type) | 56 int InterruptLevel(uint64_t softint) |
67 { | 57 { |
68 if (int_type < 0 || int_type >= num_interrupt_types) 69 panic("posting unknown interrupt!\n"); 70 if (interrupts[int_type] == false) { 71 interrupts[int_type] = true; 72 ++numPosted; 73 } | 58 if (softint & 0x10000 || softint & 0x1) 59 return 14; 60 61 int level = 15; 62 while (level > 0 && !(1 << level & softint)) 63 level--; 64 if (1 << level & softint) 65 return level; 66 return 0; |
74 } 75 76 void post(int int_num, int index) 77 { | 67 } 68 69 void post(int int_num, int index) 70 { |
71 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 72 assert(int_num >= 0 && int_num < NumInterruptTypes); 73 assert(index >= 0 && index < 64); |
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78 | 74 |
75 interrupts[int_num] |= ULL(1) << index; 76 intStatus |= ULL(1) << int_num; |
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79 } 80 81 void clear(int int_num, int index) 82 { | 77 } 78 79 void clear(int int_num, int index) 80 { |
81 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 82 assert(int_num >= 0 && int_num < NumInterruptTypes); 83 assert(index >= 0 && index < 64); |
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83 | 84 |
85 interrupts[int_num] &= ~(ULL(1) << index); 86 if (!interrupts[int_num]) 87 intStatus &= ~(ULL(1) << int_num); |
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84 } 85 86 void clear_all() 87 { | 88 } 89 90 void clear_all() 91 { |
88 | 92 for (int i = 0; i < NumInterruptTypes; ++i) { 93 interrupts[i] = 0; 94 } 95 intStatus = 0; |
89 } 90 91 bool check_interrupts(ThreadContext * tc) const 92 { | 96 } 97 98 bool check_interrupts(ThreadContext * tc) const 99 { |
93 if (numPosted) 94 return true; 95 else 96 return false; | 100 return intStatus; |
97 } 98 99 Fault getInterrupt(ThreadContext * tc) 100 { 101 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 102 int pstate = tc->readMiscReg(MISCREG_PSTATE); 103 bool ie = pstate & PSTATE::ie; 104 105 // THESE ARE IN ORDER OF PRIORITY 106 // since there are early returns, and the highest 107 // priority interrupts should get serviced, 108 // it is v. important that new interrupts are inserted 109 // in the right order of processing 110 if (hpstate & HPSTATE::hpriv) { 111 if (ie) { | 101 } 102 103 Fault getInterrupt(ThreadContext * tc) 104 { 105 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 106 int pstate = tc->readMiscReg(MISCREG_PSTATE); 107 bool ie = pstate & PSTATE::ie; 108 109 // THESE ARE IN ORDER OF PRIORITY 110 // since there are early returns, and the highest 111 // priority interrupts should get serviced, 112 // it is v. important that new interrupts are inserted 113 // in the right order of processing 114 if (hpstate & HPSTATE::hpriv) { 115 if (ie) { |
112 if (interrupts[hstick_match]) { 113 if (tc->readMiscReg(MISCREG_HINTP) & 1) { 114 interrupts[hstick_match] = false; 115 --numPosted; 116 return new HstickMatch; 117 } | 116 if (interrupts[IT_HINTP]) { 117 // This will be cleaned by a HINTP write 118 return new HstickMatch; |
118 } | 119 } |
119 if (interrupts[interrupt_vector]) { 120 interrupts[interrupt_vector] = false; 121 --numPosted; 122 //HAVEN'T IMPLed THIS YET 123 return NoFault; | 120 if (interrupts[IT_INT_VEC]) { 121 // this will be cleared by an ASI read (or write) 122 return new InterruptVector; |
124 } | 123 } |
125 } else { 126 if (interrupts[hstick_match]) { 127 return NoFault; 128 } 129 | |
130 } 131 } else { | 124 } 125 } else { |
132 if (interrupts[trap_level_zero]) { 133 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { 134 interrupts[trap_level_zero] = false; 135 --numPosted; | 126 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 127 // this is cleared by deasserting HPSTATE::tlz |
136 return new TrapLevelZero; | 128 return new TrapLevelZero; |
137 } | |
138 } | 129 } |
139 if (interrupts[hstick_match]) { 140 if (tc->readMiscReg(MISCREG_HINTP) & 1) { 141 interrupts[hstick_match] = false; 142 --numPosted; 143 return new HstickMatch; 144 } | 130 // HStick matches always happen in priv mode (ie doesn't matter) 131 if (interrupts[IT_HINTP]) { 132 return new HstickMatch; |
145 } | 133 } |
134 if (interrupts[IT_INT_VEC]) { 135 // this will be cleared by an ASI read (or write) 136 return new InterruptVector; 137 } |
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146 if (ie) { | 138 if (ie) { |
147 if (interrupts[cpu_mondo]) { 148 interrupts[cpu_mondo] = false; 149 --numPosted; | 139 if (interrupts[IT_CPU_MONDO]) { |
150 return new CpuMondo; 151 } | 140 return new CpuMondo; 141 } |
152 if (interrupts[dev_mondo]) { 153 interrupts[dev_mondo] = false; 154 --numPosted; | 142 if (interrupts[IT_DEV_MONDO]) { |
155 return new DevMondo; 156 } | 143 return new DevMondo; 144 } |
157 if (interrupts[soft_interrupt]) { 158 int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 159 // it seems that interrupt vectors are right in 160 // the middle of interrupt levels with regard to 161 // priority, so have to check 162 if ((il < 6) && 163 interrupts[interrupt_vector]) { 164 // may require more details here since there 165 // may be lots of interrupts embedded in an 166 // platform interrupt vector 167 interrupts[interrupt_vector] = false; 168 --numPosted; 169 //HAVEN'T IMPLed YET 170 return NoFault; 171 } else { 172 if (il > tc->readMiscReg(MISCREG_PIL)) { 173 uint64_t si = tc->readMiscReg(MISCREG_SOFTINT); 174 uint64_t more = si & ~(1 << (il + 1)); 175 if (!InterruptLevel(more)) { 176 interrupts[soft_interrupt] = false; 177 --numPosted; 178 } 179 return new InterruptLevelN(il); 180 } 181 } | 145 if (interrupts[IT_SOFT_INT]) { 146 return new 147 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT])); |
182 } | 148 } |
183 if (interrupts[resumable_error]) { 184 interrupts[resumable_error] = false; 185 --numPosted; | 149 150 if (interrupts[IT_RES_ERROR]) { |
186 return new ResumableError; 187 } | 151 return new ResumableError; 152 } |
188 } 189 } | 153 } // !hpriv && ie 154 } // !hpriv |
190 return NoFault; 191 } 192 193 void updateIntrInfo(ThreadContext * tc) 194 { 195 196 } 197 | 155 return NoFault; 156 } 157 158 void updateIntrInfo(ThreadContext * tc) 159 { 160 161 } 162 |
163 uint64_t get_vec(int int_num) 164 { 165 assert(int_num >= 0 && int_num < NumInterruptTypes); 166 return interrupts[int_num]; 167 } 168 |
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198 void serialize(std::ostream &os) 199 { | 169 void serialize(std::ostream &os) 170 { |
200 SERIALIZE_ARRAY(interrupts,num_interrupt_types); 201 SERIALIZE_SCALAR(numPosted); | 171 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 172 SERIALIZE_SCALAR(intStatus); |
202 } 203 204 void unserialize(Checkpoint *cp, const std::string §ion) 205 { | 173 } 174 175 void unserialize(Checkpoint *cp, const std::string §ion) 176 { |
206 UNSERIALIZE_ARRAY(interrupts,num_interrupt_types); 207 UNSERIALIZE_SCALAR(numPosted); | 177 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 178 UNSERIALIZE_SCALAR(intStatus); |
208 } 209}; 210} // namespace SPARC_ISA 211 212#endif // __ARCH_SPARC_INTERRUPT_HH__ | 179 } 180}; 181} // namespace SPARC_ISA 182 183#endif // __ARCH_SPARC_INTERRUPT_HH__ |