interrupts.hh (3894:60a7b0a3602f) | interrupts.hh (3896:182be4779097) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Gabe Black | |
29 */ 30 31#ifndef __ARCH_SPARC_INTERRUPT_HH__ 32#define __ARCH_SPARC_INTERRUPT_HH__ 33 34#include "arch/sparc/faults.hh" 35#include "cpu/thread_context.hh" 36 --- 82 unchanged lines hidden (view full) --- 119 --numPosted; 120 //HAVEN'T IMPLed THIS YET 121 return NoFault; 122 } 123 } 124 } else { 125 126 if (interrupts[trap_level_zero]) { | 27 */ 28 29#ifndef __ARCH_SPARC_INTERRUPT_HH__ 30#define __ARCH_SPARC_INTERRUPT_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "cpu/thread_context.hh" 34 --- 82 unchanged lines hidden (view full) --- 117 --numPosted; 118 //HAVEN'T IMPLed THIS YET 119 return NoFault; 120 } 121 } 122 } else { 123 124 if (interrupts[trap_level_zero]) { |
127 //HAVEN'T IMPLed YET | |
128 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { 129 interrupts[trap_level_zero] = false; 130 --numPosted; | 125 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) { 126 interrupts[trap_level_zero] = false; 127 --numPosted; |
131 return NoFault; | 128 return new TrapLevelZero; |
132 } 133 } 134 if (interrupts[hstick_match]) { 135 interrupts[hstick_match] = false; 136 --numPosted; 137 return new HstickMatch; 138 } 139 if (ie) { --- 36 unchanged lines hidden (view full) --- 176 if (interrupts[resumable_error]) { 177 interrupts[resumable_error] = false; 178 --numPosted; 179 return new ResumableError; 180 } 181 } 182 } 183 return NoFault; | 129 } 130 } 131 if (interrupts[hstick_match]) { 132 interrupts[hstick_match] = false; 133 --numPosted; 134 return new HstickMatch; 135 } 136 if (ie) { --- 36 unchanged lines hidden (view full) --- 173 if (interrupts[resumable_error]) { 174 interrupts[resumable_error] = false; 175 --numPosted; 176 return new ResumableError; 177 } 178 } 179 } 180 return NoFault; |
184 185 186 // conditioning the softint interrups 187 if (tc->readMiscReg(MISCREG_HPSTATE) & HPSTATE::hpriv) { 188 // if running in privileged mode, then pend the interrupt 189 return NoFault; 190 } else { 191 int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT)); 192 if ((int_level <= tc->readMiscReg(MISCREG_PIL)) || 193 !(tc->readMiscReg(MISCREG_PSTATE) & PSTATE::ie)) { 194 // if PIL or no interrupt enabled, then pend the interrupt 195 return NoFault; 196 } else { 197 return new InterruptLevelN(int_level); 198 } 199 } | |
200 } 201 202 void updateIntrInfo(ThreadContext * tc) 203 { 204 205 } 206 207 void serialize(std::ostream &os) 208 { 209 } 210 211 void unserialize(Checkpoint *cp, const std::string §ion) 212 { 213 } 214 }; 215} 216 217#endif // __ARCH_SPARC_INTERRUPT_HH__ | 181 } 182 183 void updateIntrInfo(ThreadContext * tc) 184 { 185 186 } 187 188 void serialize(std::ostream &os) 189 { 190 } 191 192 void unserialize(Checkpoint *cp, const std::string §ion) 193 { 194 } 195 }; 196} 197 198#endif // __ARCH_SPARC_INTERRUPT_HH__ |