interrupts.hh (11566:b11410957c9e) interrupts.hh (13912:53531772924f)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "cpu/thread_context.hh"
39#include "debug/Interrupt.hh"
40#include "params/SparcInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace SparcISA
44{
45
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 29 unchanged lines hidden (view full) ---

38#include "cpu/thread_context.hh"
39#include "debug/Interrupt.hh"
40#include "params/SparcInterrupts.hh"
41#include "sim/sim_object.hh"
42
43namespace SparcISA
44{
45
46enum InterruptTypes
47{
48 IT_TRAP_LEVEL_ZERO,
49 IT_HINTP,
50 IT_INT_VEC,
51 IT_CPU_MONDO,
52 IT_DEV_MONDO,
53 IT_RES_ERROR,
54 IT_SOFT_INT,
55 NumInterruptTypes
56};
57
46class Interrupts : public SimObject
47{
48 private:
49 BaseCPU * cpu;
50
51 uint64_t interrupts[NumInterruptTypes];
52 uint64_t intStatus;
53

--- 210 unchanged lines hidden --- 		58class Interrupts : public SimObject
59{
60 private:
61 BaseCPU * cpu;
62
63 uint64_t interrupts[NumInterruptTypes];
64 uint64_t intStatus;
65

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