interrupts.hh (11168:f98eb2da15a4) interrupts.hh (11566:b11410957c9e)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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116 interrupts[i] = 0;
117 }
118 intStatus = 0;
119 }
120
121 bool
122 checkInterrupts(ThreadContext *tc) const
123 {
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 107 unchanged lines hidden (view full) ---

116 interrupts[i] = 0;
117 }
118 intStatus = 0;
119 }
120
121 bool
122 checkInterrupts(ThreadContext *tc) const
123 {
124 return intStatus;
124 if (!intStatus)
125 return false;
126
127 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
128 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
129
130 // THESE ARE IN ORDER OF PRIORITY
131 // since there are early returns, and the highest
132 // priority interrupts should get serviced,
133 // it is v. important that new interrupts are inserted
134 // in the right order of processing
135 if (hpstate.hpriv) {
136 if (pstate.ie) {
137 if (interrupts[IT_HINTP]) {
138 // This will be cleaned by a HINTP write
139 return true;
140 }
141 if (interrupts[IT_INT_VEC]) {
142 // this will be cleared by an ASI read (or write)
143 return true;
144 }
145 }
146 } else {
147 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
148 // this is cleared by deasserting HPSTATE::tlz
149 return true;
150 }
151 // HStick matches always happen in priv mode (ie doesn't matter)
152 if (interrupts[IT_HINTP]) {
153 return true;
154 }
155 if (interrupts[IT_INT_VEC]) {
156 // this will be cleared by an ASI read (or write)
157 return true;
158 }
159 if (pstate.ie) {
160 if (interrupts[IT_CPU_MONDO]) {
161 return true;
162 }
163 if (interrupts[IT_DEV_MONDO]) {
164 return true;
165 }
166 if (interrupts[IT_SOFT_INT]) {
167 return true;
168 }
169
170 if (interrupts[IT_RES_ERROR]) {
171 return true;
172 }
173 } // !hpriv && pstate.ie
174 } // !hpriv
175
176 return false;
125 }
126
127 Fault
128 getInterrupt(ThreadContext *tc)
129 {
177 }
178
179 Fault
180 getInterrupt(ThreadContext *tc)
181 {
182 assert(checkInterrupts(tc));
183
130 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
131 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
132
133 // THESE ARE IN ORDER OF PRIORITY
134 // since there are early returns, and the highest
135 // priority interrupts should get serviced,
136 // it is v. important that new interrupts are inserted
137 // in the right order of processing

--- 72 unchanged lines hidden --- 		184 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
185 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
186
187 // THESE ARE IN ORDER OF PRIORITY
188 // since there are early returns, and the highest
189 // priority interrupts should get serviced,
190 // it is v. important that new interrupts are inserted
191 // in the right order of processing

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