1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu |
30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh"
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36#include "arch/sparc/isa_traits.hh" |
37#include "cpu/thread_context.hh" 38 39namespace SparcISA 40{ 41
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38enum interrupts_t {
39 trap_level_zero,
40 hstick_match,
41 interrupt_vector,
42 cpu_mondo,
43 dev_mondo,
44 resumable_error,
45 soft_interrupt,
46 num_interrupt_types
47};
48
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42class Interrupts 43{ 44 45 private: 46
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54 bool interrupts[num_interrupt_types];
55 int numPosted;
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47 uint64_t interrupts[NumInterruptTypes]; 48 uint64_t intStatus; |
49 50 public: 51 Interrupts() 52 {
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60 for (int i = 0; i < num_interrupt_types; ++i) {
61 interrupts[i] = false;
62 }
63 numPosted = 0;
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53 clear_all(); |
54 } 55
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66 void post(int int_type)
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56 int InterruptLevel(uint64_t softint) |
57 {
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68 if (int_type < 0 || int_type >= num_interrupt_types)
69 panic("posting unknown interrupt!\n");
70 if (interrupts[int_type] == false) {
71 interrupts[int_type] = true;
72 ++numPosted;
73 }
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58 if (softint & 0x10000 || softint & 0x1) 59 return 14; 60 61 int level = 15; 62 while (level > 0 && !(1 << level & softint)) 63 level--; 64 if (1 << level & softint) 65 return level; 66 return 0; |
67 } 68 69 void post(int int_num, int index) 70 {
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71 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 72 assert(int_num >= 0 && int_num < NumInterruptTypes); 73 assert(index >= 0 && index < 64); |
74
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75 interrupts[int_num] |= ULL(1) << index; 76 intStatus |= ULL(1) << int_num; |
77 } 78 79 void clear(int int_num, int index) 80 {
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81 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 82 assert(int_num >= 0 && int_num < NumInterruptTypes); 83 assert(index >= 0 && index < 64); |
84
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85 interrupts[int_num] &= ~(ULL(1) << index); 86 if (!interrupts[int_num]) 87 intStatus &= ~(ULL(1) << int_num); |
88 } 89 90 void clear_all() 91 {
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88
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92 for (int i = 0; i < NumInterruptTypes; ++i) { 93 interrupts[i] = 0; 94 } 95 intStatus = 0; |
96 } 97 98 bool check_interrupts(ThreadContext * tc) const 99 {
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93 if (numPosted)
94 return true;
95 else
96 return false;
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100 return intStatus; |
101 } 102 103 Fault getInterrupt(ThreadContext * tc) 104 { 105 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 106 int pstate = tc->readMiscReg(MISCREG_PSTATE); 107 bool ie = pstate & PSTATE::ie; 108 109 // THESE ARE IN ORDER OF PRIORITY 110 // since there are early returns, and the highest 111 // priority interrupts should get serviced, 112 // it is v. important that new interrupts are inserted 113 // in the right order of processing 114 if (hpstate & HPSTATE::hpriv) { 115 if (ie) {
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112 if (interrupts[hstick_match]) {
113 if (tc->readMiscReg(MISCREG_HINTP) & 1) {
114 interrupts[hstick_match] = false;
115 --numPosted;
116 return new HstickMatch;
117 }
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116 if (interrupts[IT_HINTP]) { 117 // This will be cleaned by a HINTP write 118 return new HstickMatch; |
119 }
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119 if (interrupts[interrupt_vector]) {
120 interrupts[interrupt_vector] = false;
121 --numPosted;
122 //HAVEN'T IMPLed THIS YET
123 return NoFault;
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120 if (interrupts[IT_INT_VEC]) { 121 // this will be cleared by an ASI read (or write) 122 return new InterruptVector; |
123 }
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125 } else {
126 if (interrupts[hstick_match]) {
127 return NoFault;
128 }
129
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124 } 125 } else {
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132 if (interrupts[trap_level_zero]) {
133 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
134 interrupts[trap_level_zero] = false;
135 --numPosted;
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126 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 127 // this is cleared by deasserting HPSTATE::tlz |
128 return new TrapLevelZero;
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137 }
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129 }
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139 if (interrupts[hstick_match]) {
140 if (tc->readMiscReg(MISCREG_HINTP) & 1) {
141 interrupts[hstick_match] = false;
142 --numPosted;
143 return new HstickMatch;
144 }
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130 // HStick matches always happen in priv mode (ie doesn't matter) 131 if (interrupts[IT_HINTP]) { 132 return new HstickMatch; |
133 }
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134 if (interrupts[IT_INT_VEC]) { 135 // this will be cleared by an ASI read (or write) 136 return new InterruptVector; 137 } |
138 if (ie) {
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147 if (interrupts[cpu_mondo]) {
148 interrupts[cpu_mondo] = false;
149 --numPosted;
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139 if (interrupts[IT_CPU_MONDO]) { |
140 return new CpuMondo; 141 }
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152 if (interrupts[dev_mondo]) {
153 interrupts[dev_mondo] = false;
154 --numPosted;
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142 if (interrupts[IT_DEV_MONDO]) { |
143 return new DevMondo; 144 }
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157 if (interrupts[soft_interrupt]) {
158 int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
159 // it seems that interrupt vectors are right in
160 // the middle of interrupt levels with regard to
161 // priority, so have to check
162 if ((il < 6) &&
163 interrupts[interrupt_vector]) {
164 // may require more details here since there
165 // may be lots of interrupts embedded in an
166 // platform interrupt vector
167 interrupts[interrupt_vector] = false;
168 --numPosted;
169 //HAVEN'T IMPLed YET
170 return NoFault;
171 } else {
172 if (il > tc->readMiscReg(MISCREG_PIL)) {
173 uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
174 uint64_t more = si & ~(1 << (il + 1));
175 if (!InterruptLevel(more)) {
176 interrupts[soft_interrupt] = false;
177 --numPosted;
178 }
179 return new InterruptLevelN(il);
180 }
181 }
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145 if (interrupts[IT_SOFT_INT]) { 146 return new 147 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT])); |
148 }
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183 if (interrupts[resumable_error]) {
184 interrupts[resumable_error] = false;
185 --numPosted;
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149 150 if (interrupts[IT_RES_ERROR]) { |
151 return new ResumableError; 152 }
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188 }
189 }
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153 } // !hpriv && ie 154 } // !hpriv |
155 return NoFault; 156 } 157 158 void updateIntrInfo(ThreadContext * tc) 159 { 160 161 } 162
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163 uint64_t get_vec(int int_num) 164 { 165 assert(int_num >= 0 && int_num < NumInterruptTypes); 166 return interrupts[int_num]; 167 } 168 |
169 void serialize(std::ostream &os) 170 {
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200 SERIALIZE_ARRAY(interrupts,num_interrupt_types);
201 SERIALIZE_SCALAR(numPosted);
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171 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 172 SERIALIZE_SCALAR(intStatus); |
173 } 174 175 void unserialize(Checkpoint *cp, const std::string §ion) 176 {
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206 UNSERIALIZE_ARRAY(interrupts,num_interrupt_types);
207 UNSERIALIZE_SCALAR(numPosted);
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177 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 178 UNSERIALIZE_SCALAR(intStatus); |
179 } 180}; 181} // namespace SPARC_ISA 182 183#endif // __ARCH_SPARC_INTERRUPT_HH__
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