1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "arch/sparc/registers.hh" 38#include "cpu/thread_context.hh" |
39#include "debug/Interrupt.hh" |
40#include "params/SparcInterrupts.hh" 41#include "sim/sim_object.hh" 42 43namespace SparcISA 44{ 45 46class Interrupts : public SimObject 47{ --- 163 unchanged lines hidden --- |