1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 * Lisa Hsu 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh" |
37#include "arch/sparc/miscregfile.hh" |
38#include "cpu/thread_context.hh" 39#include "params/SparcInterrupts.hh" 40#include "sim/sim_object.hh" 41 42namespace SparcISA 43{ 44 45class Interrupts : public SimObject --- 166 unchanged lines hidden --- |