1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh"
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh"
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37#include "cpu/thread_context.hh" 38#include "params/SparcInterrupts.hh" 39#include "sim/sim_object.hh" 40 41namespace SparcISA 42{ 43 44class Interrupts : public SimObject 45{ 46 private: 47 BaseCPU * cpu; 48 49 uint64_t interrupts[NumInterruptTypes]; 50 uint64_t intStatus; 51 52 public: 53 54 void 55 setCPU(BaseCPU * _cpu) 56 { 57 cpu = _cpu; 58 } 59 60 typedef SparcInterruptsParams Params; 61 62 const Params * 63 params() const 64 { 65 return dynamic_cast<const Params *>(_params); 66 } 67 68 Interrupts(Params * p) : SimObject(p), cpu(NULL) 69 { 70 clearAll(); 71 } 72 73 int 74 InterruptLevel(uint64_t softint) 75 { 76 if (softint & 0x10000 || softint & 0x1) 77 return 14; 78 79 int level = 15; 80 while (level > 0 && !(1 << level & softint)) 81 level--; 82 if (1 << level & softint) 83 return level; 84 return 0; 85 } 86 87 void 88 post(int int_num, int index) 89 { 90 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 91 assert(int_num >= 0 && int_num < NumInterruptTypes); 92 assert(index >= 0 && index < 64); 93 94 interrupts[int_num] |= ULL(1) << index; 95 intStatus |= ULL(1) << int_num; 96 } 97 98 void 99 clear(int int_num, int index) 100 { 101 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 102 assert(int_num >= 0 && int_num < NumInterruptTypes); 103 assert(index >= 0 && index < 64); 104 105 interrupts[int_num] &= ~(ULL(1) << index); 106 if (!interrupts[int_num]) 107 intStatus &= ~(ULL(1) << int_num); 108 } 109 110 void 111 clearAll() 112 { 113 for (int i = 0; i < NumInterruptTypes; ++i) { 114 interrupts[i] = 0; 115 } 116 intStatus = 0; 117 } 118 119 bool 120 checkInterrupts(ThreadContext *tc) const 121 { 122 return intStatus; 123 } 124 125 Fault 126 getInterrupt(ThreadContext *tc) 127 { 128 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 129 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 130 bool ie = pstate & PSTATE::ie; 131 132 // THESE ARE IN ORDER OF PRIORITY 133 // since there are early returns, and the highest 134 // priority interrupts should get serviced, 135 // it is v. important that new interrupts are inserted 136 // in the right order of processing 137 if (hpstate & HPSTATE::hpriv) { 138 if (ie) { 139 if (interrupts[IT_HINTP]) { 140 // This will be cleaned by a HINTP write 141 return new HstickMatch; 142 } 143 if (interrupts[IT_INT_VEC]) { 144 // this will be cleared by an ASI read (or write) 145 return new InterruptVector; 146 } 147 } 148 } else { 149 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 150 // this is cleared by deasserting HPSTATE::tlz 151 return new TrapLevelZero; 152 } 153 // HStick matches always happen in priv mode (ie doesn't matter) 154 if (interrupts[IT_HINTP]) { 155 return new HstickMatch; 156 } 157 if (interrupts[IT_INT_VEC]) { 158 // this will be cleared by an ASI read (or write) 159 return new InterruptVector; 160 } 161 if (ie) { 162 if (interrupts[IT_CPU_MONDO]) { 163 return new CpuMondo; 164 } 165 if (interrupts[IT_DEV_MONDO]) { 166 return new DevMondo; 167 } 168 if (interrupts[IT_SOFT_INT]) { 169 int level = InterruptLevel(interrupts[IT_SOFT_INT]); 170 return new InterruptLevelN(level); 171 } 172 173 if (interrupts[IT_RES_ERROR]) { 174 return new ResumableError; 175 } 176 } // !hpriv && ie 177 } // !hpriv 178 return NoFault; 179 } 180 181 void 182 updateIntrInfo(ThreadContext *tc) 183 { 184 185 } 186 187 uint64_t 188 get_vec(int int_num) 189 { 190 assert(int_num >= 0 && int_num < NumInterruptTypes); 191 return interrupts[int_num]; 192 } 193 194 void 195 serialize(std::ostream &os) 196 { 197 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 198 SERIALIZE_SCALAR(intStatus); 199 } 200 201 void 202 unserialize(Checkpoint *cp, const std::string §ion) 203 { 204 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 205 UNSERIALIZE_SCALAR(intStatus); 206 } 207}; 208} // namespace SPARC_ISA 209 210#endif // __ARCH_SPARC_INTERRUPT_HH__
| 38#include "cpu/thread_context.hh" 39#include "params/SparcInterrupts.hh" 40#include "sim/sim_object.hh" 41 42namespace SparcISA 43{ 44 45class Interrupts : public SimObject 46{ 47 private: 48 BaseCPU * cpu; 49 50 uint64_t interrupts[NumInterruptTypes]; 51 uint64_t intStatus; 52 53 public: 54 55 void 56 setCPU(BaseCPU * _cpu) 57 { 58 cpu = _cpu; 59 } 60 61 typedef SparcInterruptsParams Params; 62 63 const Params * 64 params() const 65 { 66 return dynamic_cast<const Params *>(_params); 67 } 68 69 Interrupts(Params * p) : SimObject(p), cpu(NULL) 70 { 71 clearAll(); 72 } 73 74 int 75 InterruptLevel(uint64_t softint) 76 { 77 if (softint & 0x10000 || softint & 0x1) 78 return 14; 79 80 int level = 15; 81 while (level > 0 && !(1 << level & softint)) 82 level--; 83 if (1 << level & softint) 84 return level; 85 return 0; 86 } 87 88 void 89 post(int int_num, int index) 90 { 91 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 92 assert(int_num >= 0 && int_num < NumInterruptTypes); 93 assert(index >= 0 && index < 64); 94 95 interrupts[int_num] |= ULL(1) << index; 96 intStatus |= ULL(1) << int_num; 97 } 98 99 void 100 clear(int int_num, int index) 101 { 102 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 103 assert(int_num >= 0 && int_num < NumInterruptTypes); 104 assert(index >= 0 && index < 64); 105 106 interrupts[int_num] &= ~(ULL(1) << index); 107 if (!interrupts[int_num]) 108 intStatus &= ~(ULL(1) << int_num); 109 } 110 111 void 112 clearAll() 113 { 114 for (int i = 0; i < NumInterruptTypes; ++i) { 115 interrupts[i] = 0; 116 } 117 intStatus = 0; 118 } 119 120 bool 121 checkInterrupts(ThreadContext *tc) const 122 { 123 return intStatus; 124 } 125 126 Fault 127 getInterrupt(ThreadContext *tc) 128 { 129 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 130 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 131 bool ie = pstate & PSTATE::ie; 132 133 // THESE ARE IN ORDER OF PRIORITY 134 // since there are early returns, and the highest 135 // priority interrupts should get serviced, 136 // it is v. important that new interrupts are inserted 137 // in the right order of processing 138 if (hpstate & HPSTATE::hpriv) { 139 if (ie) { 140 if (interrupts[IT_HINTP]) { 141 // This will be cleaned by a HINTP write 142 return new HstickMatch; 143 } 144 if (interrupts[IT_INT_VEC]) { 145 // this will be cleared by an ASI read (or write) 146 return new InterruptVector; 147 } 148 } 149 } else { 150 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 151 // this is cleared by deasserting HPSTATE::tlz 152 return new TrapLevelZero; 153 } 154 // HStick matches always happen in priv mode (ie doesn't matter) 155 if (interrupts[IT_HINTP]) { 156 return new HstickMatch; 157 } 158 if (interrupts[IT_INT_VEC]) { 159 // this will be cleared by an ASI read (or write) 160 return new InterruptVector; 161 } 162 if (ie) { 163 if (interrupts[IT_CPU_MONDO]) { 164 return new CpuMondo; 165 } 166 if (interrupts[IT_DEV_MONDO]) { 167 return new DevMondo; 168 } 169 if (interrupts[IT_SOFT_INT]) { 170 int level = InterruptLevel(interrupts[IT_SOFT_INT]); 171 return new InterruptLevelN(level); 172 } 173 174 if (interrupts[IT_RES_ERROR]) { 175 return new ResumableError; 176 } 177 } // !hpriv && ie 178 } // !hpriv 179 return NoFault; 180 } 181 182 void 183 updateIntrInfo(ThreadContext *tc) 184 { 185 186 } 187 188 uint64_t 189 get_vec(int int_num) 190 { 191 assert(int_num >= 0 && int_num < NumInterruptTypes); 192 return interrupts[int_num]; 193 } 194 195 void 196 serialize(std::ostream &os) 197 { 198 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 199 SERIALIZE_SCALAR(intStatus); 200 } 201 202 void 203 unserialize(Checkpoint *cp, const std::string §ion) 204 { 205 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 206 UNSERIALIZE_SCALAR(intStatus); 207 } 208}; 209} // namespace SPARC_ISA 210 211#endif // __ARCH_SPARC_INTERRUPT_HH__
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