1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "cpu/thread_context.hh" 38#include "params/SparcInterrupts.hh" 39#include "sim/sim_object.hh" 40 41namespace SparcISA 42{ 43 44class Interrupts : public SimObject 45{ 46 47 private:
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Lisa Hsu 30 */ 31 32#ifndef __ARCH_SPARC_INTERRUPT_HH__ 33#define __ARCH_SPARC_INTERRUPT_HH__ 34 35#include "arch/sparc/faults.hh" 36#include "arch/sparc/isa_traits.hh" 37#include "cpu/thread_context.hh" 38#include "params/SparcInterrupts.hh" 39#include "sim/sim_object.hh" 40 41namespace SparcISA 42{ 43 44class Interrupts : public SimObject 45{ 46 47 private:
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48
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49 uint64_t interrupts[NumInterruptTypes]; 50 uint64_t intStatus; 51 52 public: 53 typedef SparcInterruptsParams Params; 54 55 const Params * 56 params() const 57 { 58 return dynamic_cast<const Params *>(_params); 59 } 60 61 Interrupts(Params * p) : SimObject(p) 62 {
| 48 uint64_t interrupts[NumInterruptTypes]; 49 uint64_t intStatus; 50 51 public: 52 typedef SparcInterruptsParams Params; 53 54 const Params * 55 params() const 56 { 57 return dynamic_cast<const Params *>(_params); 58 } 59 60 Interrupts(Params * p) : SimObject(p) 61 {
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63 clear_all();
| 62 clearAll();
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64 } 65
| 63 } 64
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66 int InterruptLevel(uint64_t softint)
| 65 int 66 InterruptLevel(uint64_t softint)
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67 { 68 if (softint & 0x10000 || softint & 0x1) 69 return 14; 70 71 int level = 15; 72 while (level > 0 && !(1 << level & softint)) 73 level--; 74 if (1 << level & softint) 75 return level; 76 return 0; 77 } 78
| 67 { 68 if (softint & 0x10000 || softint & 0x1) 69 return 14; 70 71 int level = 15; 72 while (level > 0 && !(1 << level & softint)) 73 level--; 74 if (1 << level & softint) 75 return level; 76 return 0; 77 } 78
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79 void post(int int_num, int index)
| 79 void 80 post(int int_num, int index)
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80 { 81 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 82 assert(int_num >= 0 && int_num < NumInterruptTypes); 83 assert(index >= 0 && index < 64); 84 85 interrupts[int_num] |= ULL(1) << index; 86 intStatus |= ULL(1) << int_num; 87 } 88
| 81 { 82 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 83 assert(int_num >= 0 && int_num < NumInterruptTypes); 84 assert(index >= 0 && index < 64); 85 86 interrupts[int_num] |= ULL(1) << index; 87 intStatus |= ULL(1) << int_num; 88 } 89
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89 void clear(int int_num, int index)
| 90 void 91 clear(int int_num, int index)
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90 { 91 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 92 assert(int_num >= 0 && int_num < NumInterruptTypes); 93 assert(index >= 0 && index < 64); 94 95 interrupts[int_num] &= ~(ULL(1) << index); 96 if (!interrupts[int_num]) 97 intStatus &= ~(ULL(1) << int_num); 98 } 99
| 92 { 93 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 94 assert(int_num >= 0 && int_num < NumInterruptTypes); 95 assert(index >= 0 && index < 64); 96 97 interrupts[int_num] &= ~(ULL(1) << index); 98 if (!interrupts[int_num]) 99 intStatus &= ~(ULL(1) << int_num); 100 } 101
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100 void clear_all()
| 102 void 103 clearAll()
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101 { 102 for (int i = 0; i < NumInterruptTypes; ++i) { 103 interrupts[i] = 0; 104 } 105 intStatus = 0; 106 } 107
| 104 { 105 for (int i = 0; i < NumInterruptTypes; ++i) { 106 interrupts[i] = 0; 107 } 108 intStatus = 0; 109 } 110
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108 bool check_interrupts(ThreadContext * tc) const
| 111 bool 112 checkInterrupts(ThreadContext *tc) const
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109 { 110 return intStatus; 111 } 112
| 113 { 114 return intStatus; 115 } 116
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113 Fault getInterrupt(ThreadContext * tc)
| 117 Fault 118 getInterrupt(ThreadContext *tc)
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114 { 115 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 116 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 117 bool ie = pstate & PSTATE::ie; 118 119 // THESE ARE IN ORDER OF PRIORITY 120 // since there are early returns, and the highest 121 // priority interrupts should get serviced, 122 // it is v. important that new interrupts are inserted 123 // in the right order of processing 124 if (hpstate & HPSTATE::hpriv) { 125 if (ie) { 126 if (interrupts[IT_HINTP]) { 127 // This will be cleaned by a HINTP write 128 return new HstickMatch; 129 } 130 if (interrupts[IT_INT_VEC]) { 131 // this will be cleared by an ASI read (or write) 132 return new InterruptVector; 133 } 134 } 135 } else { 136 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 137 // this is cleared by deasserting HPSTATE::tlz 138 return new TrapLevelZero; 139 } 140 // HStick matches always happen in priv mode (ie doesn't matter) 141 if (interrupts[IT_HINTP]) { 142 return new HstickMatch; 143 } 144 if (interrupts[IT_INT_VEC]) { 145 // this will be cleared by an ASI read (or write) 146 return new InterruptVector; 147 } 148 if (ie) { 149 if (interrupts[IT_CPU_MONDO]) { 150 return new CpuMondo; 151 } 152 if (interrupts[IT_DEV_MONDO]) { 153 return new DevMondo; 154 } 155 if (interrupts[IT_SOFT_INT]) {
| 119 { 120 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 121 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 122 bool ie = pstate & PSTATE::ie; 123 124 // THESE ARE IN ORDER OF PRIORITY 125 // since there are early returns, and the highest 126 // priority interrupts should get serviced, 127 // it is v. important that new interrupts are inserted 128 // in the right order of processing 129 if (hpstate & HPSTATE::hpriv) { 130 if (ie) { 131 if (interrupts[IT_HINTP]) { 132 // This will be cleaned by a HINTP write 133 return new HstickMatch; 134 } 135 if (interrupts[IT_INT_VEC]) { 136 // this will be cleared by an ASI read (or write) 137 return new InterruptVector; 138 } 139 } 140 } else { 141 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 142 // this is cleared by deasserting HPSTATE::tlz 143 return new TrapLevelZero; 144 } 145 // HStick matches always happen in priv mode (ie doesn't matter) 146 if (interrupts[IT_HINTP]) { 147 return new HstickMatch; 148 } 149 if (interrupts[IT_INT_VEC]) { 150 // this will be cleared by an ASI read (or write) 151 return new InterruptVector; 152 } 153 if (ie) { 154 if (interrupts[IT_CPU_MONDO]) { 155 return new CpuMondo; 156 } 157 if (interrupts[IT_DEV_MONDO]) { 158 return new DevMondo; 159 } 160 if (interrupts[IT_SOFT_INT]) {
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156 return new 157 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
| 161 int level = InterruptLevel(interrupts[IT_SOFT_INT]); 162 return new InterruptLevelN(level);
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158 } 159 160 if (interrupts[IT_RES_ERROR]) { 161 return new ResumableError; 162 } 163 } // !hpriv && ie 164 } // !hpriv 165 return NoFault; 166 } 167
| 163 } 164 165 if (interrupts[IT_RES_ERROR]) { 166 return new ResumableError; 167 } 168 } // !hpriv && ie 169 } // !hpriv 170 return NoFault; 171 } 172
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168 void updateIntrInfo(ThreadContext * tc)
| 173 void 174 updateIntrInfo(ThreadContext *tc)
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169 { 170 171 } 172
| 175 { 176 177 } 178
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173 uint64_t get_vec(int int_num)
| 179 uint64_t 180 get_vec(int int_num)
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174 { 175 assert(int_num >= 0 && int_num < NumInterruptTypes); 176 return interrupts[int_num]; 177 } 178
| 181 { 182 assert(int_num >= 0 && int_num < NumInterruptTypes); 183 return interrupts[int_num]; 184 } 185
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179 void serialize(std::ostream &os)
| 186 void 187 serialize(std::ostream &os)
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180 { 181 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 182 SERIALIZE_SCALAR(intStatus); 183 } 184
| 188 { 189 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 190 SERIALIZE_SCALAR(intStatus); 191 } 192
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185 void unserialize(Checkpoint *cp, const std::string §ion)
| 193 void 194 unserialize(Checkpoint *cp, const std::string §ion)
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186 { 187 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 188 UNSERIALIZE_SCALAR(intStatus); 189 } 190}; 191} // namespace SPARC_ISA 192 193#endif // __ARCH_SPARC_INTERRUPT_HH__
| 195 { 196 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 197 UNSERIALIZE_SCALAR(intStatus); 198 } 199}; 200} // namespace SPARC_ISA 201 202#endif // __ARCH_SPARC_INTERRUPT_HH__
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