1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Lisa Hsu
30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "cpu/thread_context.hh"
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 * Lisa Hsu
30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "cpu/thread_context.hh"
|
| 38#include "params/SparcInterrupts.hh"
39#include "sim/sim_object.hh"
|
38
39namespace SparcISA
40{
41
| 40
41namespace SparcISA
42{
43
|
42class Interrupts
| 44class Interrupts : public SimObject
|
43{
44
45 private:
46
47 uint64_t interrupts[NumInterruptTypes];
48 uint64_t intStatus;
49
50 public:
| 45{
46
47 private:
48
49 uint64_t interrupts[NumInterruptTypes];
50 uint64_t intStatus;
51
52 public:
|
51 Interrupts()
| 53 typedef SparcInterruptsParams Params;
54
55 const Params *
56 params() const
|
52 {
| 57 {
|
| 58 return dynamic_cast<const Params *>(_params);
59 }
60
61 Interrupts(Params * p) : SimObject(p)
62 {
|
53 clear_all();
54 }
55
56 int InterruptLevel(uint64_t softint)
57 {
58 if (softint & 0x10000 || softint & 0x1)
59 return 14;
60
61 int level = 15;
62 while (level > 0 && !(1 << level & softint))
63 level--;
64 if (1 << level & softint)
65 return level;
66 return 0;
67 }
68
69 void post(int int_num, int index)
70 {
71 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
72 assert(int_num >= 0 && int_num < NumInterruptTypes);
73 assert(index >= 0 && index < 64);
74
75 interrupts[int_num] |= ULL(1) << index;
76 intStatus |= ULL(1) << int_num;
77 }
78
79 void clear(int int_num, int index)
80 {
81 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
82 assert(int_num >= 0 && int_num < NumInterruptTypes);
83 assert(index >= 0 && index < 64);
84
85 interrupts[int_num] &= ~(ULL(1) << index);
86 if (!interrupts[int_num])
87 intStatus &= ~(ULL(1) << int_num);
88 }
89
90 void clear_all()
91 {
92 for (int i = 0; i < NumInterruptTypes; ++i) {
93 interrupts[i] = 0;
94 }
95 intStatus = 0;
96 }
97
98 bool check_interrupts(ThreadContext * tc) const
99 {
100 return intStatus;
101 }
102
103 Fault getInterrupt(ThreadContext * tc)
104 {
105 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
106 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
107 bool ie = pstate & PSTATE::ie;
108
109 // THESE ARE IN ORDER OF PRIORITY
110 // since there are early returns, and the highest
111 // priority interrupts should get serviced,
112 // it is v. important that new interrupts are inserted
113 // in the right order of processing
114 if (hpstate & HPSTATE::hpriv) {
115 if (ie) {
116 if (interrupts[IT_HINTP]) {
117 // This will be cleaned by a HINTP write
118 return new HstickMatch;
119 }
120 if (interrupts[IT_INT_VEC]) {
121 // this will be cleared by an ASI read (or write)
122 return new InterruptVector;
123 }
124 }
125 } else {
126 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
127 // this is cleared by deasserting HPSTATE::tlz
128 return new TrapLevelZero;
129 }
130 // HStick matches always happen in priv mode (ie doesn't matter)
131 if (interrupts[IT_HINTP]) {
132 return new HstickMatch;
133 }
134 if (interrupts[IT_INT_VEC]) {
135 // this will be cleared by an ASI read (or write)
136 return new InterruptVector;
137 }
138 if (ie) {
139 if (interrupts[IT_CPU_MONDO]) {
140 return new CpuMondo;
141 }
142 if (interrupts[IT_DEV_MONDO]) {
143 return new DevMondo;
144 }
145 if (interrupts[IT_SOFT_INT]) {
146 return new
147 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
148 }
149
150 if (interrupts[IT_RES_ERROR]) {
151 return new ResumableError;
152 }
153 } // !hpriv && ie
154 } // !hpriv
155 return NoFault;
156 }
157
158 void updateIntrInfo(ThreadContext * tc)
159 {
160
161 }
162
163 uint64_t get_vec(int int_num)
164 {
165 assert(int_num >= 0 && int_num < NumInterruptTypes);
166 return interrupts[int_num];
167 }
168
169 void serialize(std::ostream &os)
170 {
171 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
172 SERIALIZE_SCALAR(intStatus);
173 }
174
175 void unserialize(Checkpoint *cp, const std::string §ion)
176 {
177 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
178 UNSERIALIZE_SCALAR(intStatus);
179 }
180};
181} // namespace SPARC_ISA
182
183#endif // __ARCH_SPARC_INTERRUPT_HH__
| 63 clear_all();
64 }
65
66 int InterruptLevel(uint64_t softint)
67 {
68 if (softint & 0x10000 || softint & 0x1)
69 return 14;
70
71 int level = 15;
72 while (level > 0 && !(1 << level & softint))
73 level--;
74 if (1 << level & softint)
75 return level;
76 return 0;
77 }
78
79 void post(int int_num, int index)
80 {
81 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
82 assert(int_num >= 0 && int_num < NumInterruptTypes);
83 assert(index >= 0 && index < 64);
84
85 interrupts[int_num] |= ULL(1) << index;
86 intStatus |= ULL(1) << int_num;
87 }
88
89 void clear(int int_num, int index)
90 {
91 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
92 assert(int_num >= 0 && int_num < NumInterruptTypes);
93 assert(index >= 0 && index < 64);
94
95 interrupts[int_num] &= ~(ULL(1) << index);
96 if (!interrupts[int_num])
97 intStatus &= ~(ULL(1) << int_num);
98 }
99
100 void clear_all()
101 {
102 for (int i = 0; i < NumInterruptTypes; ++i) {
103 interrupts[i] = 0;
104 }
105 intStatus = 0;
106 }
107
108 bool check_interrupts(ThreadContext * tc) const
109 {
110 return intStatus;
111 }
112
113 Fault getInterrupt(ThreadContext * tc)
114 {
115 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
116 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
117 bool ie = pstate & PSTATE::ie;
118
119 // THESE ARE IN ORDER OF PRIORITY
120 // since there are early returns, and the highest
121 // priority interrupts should get serviced,
122 // it is v. important that new interrupts are inserted
123 // in the right order of processing
124 if (hpstate & HPSTATE::hpriv) {
125 if (ie) {
126 if (interrupts[IT_HINTP]) {
127 // This will be cleaned by a HINTP write
128 return new HstickMatch;
129 }
130 if (interrupts[IT_INT_VEC]) {
131 // this will be cleared by an ASI read (or write)
132 return new InterruptVector;
133 }
134 }
135 } else {
136 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
137 // this is cleared by deasserting HPSTATE::tlz
138 return new TrapLevelZero;
139 }
140 // HStick matches always happen in priv mode (ie doesn't matter)
141 if (interrupts[IT_HINTP]) {
142 return new HstickMatch;
143 }
144 if (interrupts[IT_INT_VEC]) {
145 // this will be cleared by an ASI read (or write)
146 return new InterruptVector;
147 }
148 if (ie) {
149 if (interrupts[IT_CPU_MONDO]) {
150 return new CpuMondo;
151 }
152 if (interrupts[IT_DEV_MONDO]) {
153 return new DevMondo;
154 }
155 if (interrupts[IT_SOFT_INT]) {
156 return new
157 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
158 }
159
160 if (interrupts[IT_RES_ERROR]) {
161 return new ResumableError;
162 }
163 } // !hpriv && ie
164 } // !hpriv
165 return NoFault;
166 }
167
168 void updateIntrInfo(ThreadContext * tc)
169 {
170
171 }
172
173 uint64_t get_vec(int int_num)
174 {
175 assert(int_num >= 0 && int_num < NumInterruptTypes);
176 return interrupts[int_num];
177 }
178
179 void serialize(std::ostream &os)
180 {
181 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
182 SERIALIZE_SCALAR(intStatus);
183 }
184
185 void unserialize(Checkpoint *cp, const std::string §ion)
186 {
187 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
188 UNSERIALIZE_SCALAR(intStatus);
189 }
190};
191} // namespace SPARC_ISA
192
193#endif // __ARCH_SPARC_INTERRUPT_HH__
|