1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_INTERRUPT_HH__ 30#define __ARCH_SPARC_INTERRUPT_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "cpu/thread_context.hh" 34 35namespace SparcISA 36{ 37 38enum interrupts_t { 39 trap_level_zero, 40 hstick_match, 41 interrupt_vector, 42 cpu_mondo, 43 dev_mondo, 44 resumable_error, 45 soft_interrupt, 46 num_interrupt_types 47}; 48 49 class Interrupts 50 { 51 52 private: 53 54 bool interrupts[num_interrupt_types]; 55 int numPosted; 56 57 public: 58 Interrupts() 59 { 60 for (int i = 0; i < num_interrupt_types; ++i) { 61 interrupts[i] = false; 62 } 63 numPosted = 0; 64 } 65 66 void post(int int_type) 67 { 68 if (int_type < 0 || int_type >= num_interrupt_types) 69 panic("posting unknown interrupt!\n"); 70 interrupts[int_type] = true; 71 ++numPosted; 72 } 73 74 void post(int int_num, int index) 75 { 76 77 } 78 79 void clear(int int_num, int index) 80 { 81 82 } 83 84 void clear_all() 85 { 86 87 } 88 89 bool check_interrupts(ThreadContext * tc) const 90 { 91 if (numPosted) 92 return true; 93 else 94 return false; 95 } 96 97 Fault getInterrupt(ThreadContext * tc) 98 { 99 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 100 int pstate = tc->readMiscReg(MISCREG_PSTATE); 101 bool ie = pstate & PSTATE::ie; 102 103 // THESE ARE IN ORDER OF PRIORITY 104 // since there are early returns, and the highest 105 // priority interrupts should get serviced, 106 // it is v. important that new interrupts are inserted 107 // in the right order of processing 108 if (hpstate & HPSTATE::hpriv) { 109 if (ie) { 110 if (interrupts[hstick_match]) {
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __ARCH_SPARC_INTERRUPT_HH__ 30#define __ARCH_SPARC_INTERRUPT_HH__ 31 32#include "arch/sparc/faults.hh" 33#include "cpu/thread_context.hh" 34 35namespace SparcISA 36{ 37 38enum interrupts_t { 39 trap_level_zero, 40 hstick_match, 41 interrupt_vector, 42 cpu_mondo, 43 dev_mondo, 44 resumable_error, 45 soft_interrupt, 46 num_interrupt_types 47}; 48 49 class Interrupts 50 { 51 52 private: 53 54 bool interrupts[num_interrupt_types]; 55 int numPosted; 56 57 public: 58 Interrupts() 59 { 60 for (int i = 0; i < num_interrupt_types; ++i) { 61 interrupts[i] = false; 62 } 63 numPosted = 0; 64 } 65 66 void post(int int_type) 67 { 68 if (int_type < 0 || int_type >= num_interrupt_types) 69 panic("posting unknown interrupt!\n"); 70 interrupts[int_type] = true; 71 ++numPosted; 72 } 73 74 void post(int int_num, int index) 75 { 76 77 } 78 79 void clear(int int_num, int index) 80 { 81 82 } 83 84 void clear_all() 85 { 86 87 } 88 89 bool check_interrupts(ThreadContext * tc) const 90 { 91 if (numPosted) 92 return true; 93 else 94 return false; 95 } 96 97 Fault getInterrupt(ThreadContext * tc) 98 { 99 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 100 int pstate = tc->readMiscReg(MISCREG_PSTATE); 101 bool ie = pstate & PSTATE::ie; 102 103 // THESE ARE IN ORDER OF PRIORITY 104 // since there are early returns, and the highest 105 // priority interrupts should get serviced, 106 // it is v. important that new interrupts are inserted 107 // in the right order of processing 108 if (hpstate & HPSTATE::hpriv) { 109 if (ie) { 110 if (interrupts[hstick_match]) {
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