1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#ifndef __ARCH_SPARC_INTERRUPT_HH__
33#define __ARCH_SPARC_INTERRUPT_HH__
34
35#include "arch/sparc/faults.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "cpu/thread_context.hh"
38
39namespace SparcISA
40{
41
42class Interrupts
43{
44
45 private:
46
47 uint64_t interrupts[NumInterruptTypes];
48 uint64_t intStatus;
49
50 public:
51 Interrupts()
52 {
53 clear_all();
54 }
55
56 int InterruptLevel(uint64_t softint)
57 {
58 if (softint & 0x10000 || softint & 0x1)
59 return 14;
60

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