1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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103 // THESE ARE IN ORDER OF PRIORITY
104 // since there are early returns, and the highest
105 // priority interrupts should get serviced,
106 // it is v. important that new interrupts are inserted
107 // in the right order of processing
108 if (hpstate & HPSTATE::hpriv) {
109 if (ie) {
110 if (interrupts[hstick_match]) {
111 interrupts[hstick_match] = false;
112 --numPosted;
113 return new HstickMatch;
114 }
115 if (interrupts[interrupt_vector]) {
116 interrupts[interrupt_vector] = false;
117 --numPosted;
118 //HAVEN'T IMPLed THIS YET
119 return NoFault;
120 }
121 }
122 } else {
123
124 if (interrupts[trap_level_zero]) {
125 if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
126 interrupts[trap_level_zero] = false;
127 --numPosted;
128 return new TrapLevelZero;
129 }
130 }
131 if (interrupts[hstick_match]) {
132 interrupts[hstick_match] = false;
133 --numPosted;
134 return new HstickMatch;
135 }
136 if (ie) {
137 if (interrupts[cpu_mondo]) {
138 interrupts[cpu_mondo] = false;
139 --numPosted;
140 return new CpuMondo;
141 }
142 if (interrupts[dev_mondo]) {

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