1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved
4 * Copyright 2017 Google Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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41
42/**
43 * Base class for privelege mode operations.
44 */
45class Priv : public SparcStaticInst
46{
47 protected:
48 using SparcStaticInst::SparcStaticInst;
49 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
50};
51
52class PrivReg : public Priv
53{
54 protected:
55 PrivReg(const char *mnem, ExtMachInst _machInst,
56 OpClass __opClass, char const * _regName) :
57 Priv(mnem, _machInst, __opClass), regName(_regName)
58 {}
59
60 char const *regName;
61};
62
63// This class is for instructions that explicitly read control
64// registers. It provides a special generateDisassembly function.
65class RdPriv : public PrivReg
66{
67 protected:
68 using PrivReg::PrivReg;
69 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
70};
71
72// This class is for instructions that explicitly write control
73// registers. It provides a special generateDisassembly function.
74class WrPriv : public PrivReg
75{
76 protected:
77 using PrivReg::PrivReg;
78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
79};
80
81/**
82 * Base class for privelege mode operations with immediates.
83 */
84class PrivImm : public Priv
85{
86 protected:

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98{
99 protected:
100 // Constructor
101 WrPrivImm(const char *mnem, ExtMachInst _machInst,
102 OpClass __opClass, char const *_regName) :
103 PrivImm(mnem, _machInst, __opClass), regName(_regName)
104 {}
105
106 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
107
108 char const *regName;
109}
110;
111}
112
113#endif //__ARCH_SPARC_INSTS_PRIV_HH__