faults.cc (9551:f867e530f39b) faults.cc (10417:710ee116eb68)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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485 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
486 PC = (TBA & ~mask(15)) |
487 (TL > 1 ? (1 << 14) : 0) |
488 ((TT << 5) & mask(14));
489 NPC = PC + sizeof(MachInst);
490}
491
492void
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 476 unchanged lines hidden (view full) ---

485 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
486 PC = (TBA & ~mask(15)) |
487 (TL > 1 ? (1 << 14) : 0) |
488 ((TT << 5) & mask(14));
489 NPC = PC + sizeof(MachInst);
490}
491
492void
493SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
493SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
494{
495 FaultBase::invoke(tc);
496 if (!FullSystem)
497 return;
498
499 countStat()++;
500
501 // We can refer to this to see what the trap level -was-, but something

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546 pc.npc(NPC);
547 pc.nnpc(NPC + sizeof(MachInst));
548 pc.upc(0);
549 pc.nupc(1);
550 tc->pcState(pc);
551}
552
553void
494{
495 FaultBase::invoke(tc);
496 if (!FullSystem)
497 return;
498
499 countStat()++;
500
501 // We can refer to this to see what the trap level -was-, but something

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546 pc.npc(NPC);
547 pc.nnpc(NPC + sizeof(MachInst));
548 pc.upc(0);
549 pc.nupc(1);
550 tc->pcState(pc);
551}
552
553void
554PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
554PowerOnReset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
555{
556 // For SPARC, when a system is first started, there is a power
557 // on reset Trap which sets the processor into the following state.
558 // Bits that aren't set aren't defined on startup.
559
560 tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
561 tc->setMiscRegNoEffect(MISCREG_TT, trapType());
562 tc->setMiscReg(MISCREG_GL, MaxGL);

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609
610 hintp = 0; // no interrupts pending
611 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
612 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
613 */
614}
615
616void
555{
556 // For SPARC, when a system is first started, there is a power
557 // on reset Trap which sets the processor into the following state.
558 // Bits that aren't set aren't defined on startup.
559
560 tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
561 tc->setMiscRegNoEffect(MISCREG_TT, trapType());
562 tc->setMiscReg(MISCREG_GL, MaxGL);

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609
610 hintp = 0; // no interrupts pending
611 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
612 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
613 */
614}
615
616void
617FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
617FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
618 const StaticInstPtr &inst)
618{
619 if (FullSystem) {
620 SparcFaultBase::invoke(tc, inst);
621 return;
622 }
623
624 Process *p = tc->getProcessPtr();
625 TlbEntry entry;
626 bool success = p->pTable->lookup(vaddr, entry);
627 if (!success) {
628 panic("Tried to execute unmapped address %#x.\n", vaddr);
629 } else {
630 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
631 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
632 p->M5_pid /*context id*/, false, entry.pte);
633 }
634}
635
636void
619{
620 if (FullSystem) {
621 SparcFaultBase::invoke(tc, inst);
622 return;
623 }
624
625 Process *p = tc->getProcessPtr();
626 TlbEntry entry;
627 bool success = p->pTable->lookup(vaddr, entry);
628 if (!success) {
629 panic("Tried to execute unmapped address %#x.\n", vaddr);
630 } else {
631 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
632 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
633 p->M5_pid /*context id*/, false, entry.pte);
634 }
635}
636
637void
637FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
638FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
638{
639 if (FullSystem) {
640 SparcFaultBase::invoke(tc, inst);
641 return;
642 }
643
644 Process *p = tc->getProcessPtr();
645 TlbEntry entry;

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653 } else {
654 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
655 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
656 p->M5_pid /*context id*/, false, entry.pte);
657 }
658}
659
660void
639{
640 if (FullSystem) {
641 SparcFaultBase::invoke(tc, inst);
642 return;
643 }
644
645 Process *p = tc->getProcessPtr();
646 TlbEntry entry;

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654 } else {
655 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
656 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
657 p->M5_pid /*context id*/, false, entry.pte);
658 }
659}
660
661void
661SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
662SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
662{
663 if (FullSystem) {
664 SparcFaultBase::invoke(tc, inst);
665 return;
666 }
667
668 doNormalFault(tc, trapType(), false);
669
670 Process *p = tc->getProcessPtr();
671
672 //XXX This will only work in faults from a SparcLiveProcess
673 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
674 assert(lp);
675
676 // Then adjust the PC and NPC
677 tc->pcState(lp->readSpillStart());
678}
679
680void
663{
664 if (FullSystem) {
665 SparcFaultBase::invoke(tc, inst);
666 return;
667 }
668
669 doNormalFault(tc, trapType(), false);
670
671 Process *p = tc->getProcessPtr();
672
673 //XXX This will only work in faults from a SparcLiveProcess
674 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
675 assert(lp);
676
677 // Then adjust the PC and NPC
678 tc->pcState(lp->readSpillStart());
679}
680
681void
681FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
682FillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
682{
683 if (FullSystem) {
684 SparcFaultBase::invoke(tc, inst);
685 return;
686 }
687
688 doNormalFault(tc, trapType(), false);
689
690 Process *p = tc->getProcessPtr();
691
692 //XXX This will only work in faults from a SparcLiveProcess
693 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
694 assert(lp);
695
696 // Then adjust the PC and NPC
697 tc->pcState(lp->readFillStart());
698}
699
700void
683{
684 if (FullSystem) {
685 SparcFaultBase::invoke(tc, inst);
686 return;
687 }
688
689 doNormalFault(tc, trapType(), false);
690
691 Process *p = tc->getProcessPtr();
692
693 //XXX This will only work in faults from a SparcLiveProcess
694 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
695 assert(lp);
696
697 // Then adjust the PC and NPC
698 tc->pcState(lp->readFillStart());
699}
700
701void
701TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
702TrapInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
702{
703 if (FullSystem) {
704 SparcFaultBase::invoke(tc, inst);
705 return;
706 }
707
708 // In SE, this mechanism is how the process requests a service from
709 // the operating system. We'll get the process object from the thread

--- 18 unchanged lines hidden --- 		703{
704 if (FullSystem) {
705 SparcFaultBase::invoke(tc, inst);
706 return;
707 }
708
709 // In SE, this mechanism is how the process requests a service from
710 // the operating system. We'll get the process object from the thread

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