faults.cc (8539:7d3ea3c65c66) | faults.cc (8750:6f63141531c8) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31 32#include <algorithm> 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" 36#include "arch/sparc/types.hh" 37#include "base/bitfield.hh" 38#include "base/trace.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31 32#include <algorithm> 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" 36#include "arch/sparc/types.hh" 37#include "base/bitfield.hh" 38#include "base/trace.hh" |
39#include "config/full_system.hh" | 39#include "sim/full_system.hh" |
40#include "cpu/base.hh" 41#include "cpu/thread_context.hh" 42#if !FULL_SYSTEM 43#include "arch/sparc/process.hh" 44#include "mem/page_table.hh" 45#include "sim/process.hh" 46#endif | 40#include "cpu/base.hh" 41#include "cpu/thread_context.hh" 42#if !FULL_SYSTEM 43#include "arch/sparc/process.hh" 44#include "mem/page_table.hh" 45#include "sim/process.hh" 46#endif |
47#include "sim/full_system.hh" |
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47 48using namespace std; 49 50namespace SparcISA 51{ 52 53template<> SparcFaultBase::FaultVals 54 SparcFault<PowerOnReset>::vals = --- 434 unchanged lines hidden (view full) --- 489{ 490 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); 491 PC = (TBA & ~mask(15)) | 492 (TL > 1 ? (1 << 14) : 0) | 493 ((TT << 5) & mask(14)); 494 NPC = PC + sizeof(MachInst); 495} 496 | 48 49using namespace std; 50 51namespace SparcISA 52{ 53 54template<> SparcFaultBase::FaultVals 55 SparcFault<PowerOnReset>::vals = --- 434 unchanged lines hidden (view full) --- 490{ 491 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA); 492 PC = (TBA & ~mask(15)) | 493 (TL > 1 ? (1 << 14) : 0) | 494 ((TT << 5) & mask(14)); 495 NPC = PC + sizeof(MachInst); 496} 497 |
497#if FULL_SYSTEM 498 | |
499void 500SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) 501{ 502 FaultBase::invoke(tc); | 498void 499SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst) 500{ 501 FaultBase::invoke(tc); |
502 if (!FullSystem) 503 return; 504 |
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503 countStat()++; 504 505 // We can refer to this to see what the trap level -was-, but something 506 // in the middle could change it in the regfile out from under us. 507 MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL); 508 MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT); 509 MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 510 MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); --- 103 unchanged lines hidden (view full) --- 614 tt[tl] = _trapType; 615 616 hintp = 0; // no interrupts pending 617 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 618 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 619 */ 620} 621 | 505 countStat()++; 506 507 // We can refer to this to see what the trap level -was-, but something 508 // in the middle could change it in the regfile out from under us. 509 MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL); 510 MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT); 511 MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE); 512 MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE); --- 103 unchanged lines hidden (view full) --- 616 tt[tl] = _trapType; 617 618 hintp = 0; // no interrupts pending 619 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts 620 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing 621 */ 622} 623 |
622#else // !FULL_SYSTEM 623 | |
624void 625FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) 626{ | 624void 625FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) 626{ |
627#if !FULL_SYSTEM |
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627 Process *p = tc->getProcessPtr(); 628 TlbEntry entry; 629 bool success = p->pTable->lookup(vaddr, entry); 630 if (!success) { 631 panic("Tried to execute unmapped address %#x.\n", vaddr); 632 } else { 633 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 634 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/, 635 p->M5_pid /*context id*/, false, entry.pte); 636 } | 628 Process *p = tc->getProcessPtr(); 629 TlbEntry entry; 630 bool success = p->pTable->lookup(vaddr, entry); 631 if (!success) { 632 panic("Tried to execute unmapped address %#x.\n", vaddr); 633 } else { 634 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 635 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/, 636 p->M5_pid /*context id*/, false, entry.pte); 637 } |
638#else 639 SparcFaultBase::invoke(tc, inst); 640#endif |
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637} 638 639void 640FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) 641{ | 641} 642 643void 644FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst) 645{ |
646#if !FULL_SYSTEM |
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642 Process *p = tc->getProcessPtr(); 643 TlbEntry entry; 644 bool success = p->pTable->lookup(vaddr, entry); 645 if (!success) { 646 if (p->fixupStackFault(vaddr)) 647 success = p->pTable->lookup(vaddr, entry); 648 } 649 if (!success) { 650 panic("Tried to access unmapped address %#x.\n", vaddr); 651 } else { 652 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 653 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/, 654 p->M5_pid /*context id*/, false, entry.pte); 655 } | 647 Process *p = tc->getProcessPtr(); 648 TlbEntry entry; 649 bool success = p->pTable->lookup(vaddr, entry); 650 if (!success) { 651 if (p->fixupStackFault(vaddr)) 652 success = p->pTable->lookup(vaddr, entry); 653 } 654 if (!success) { 655 panic("Tried to access unmapped address %#x.\n", vaddr); 656 } else { 657 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 658 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/, 659 p->M5_pid /*context id*/, false, entry.pte); 660 } |
661#else 662 SparcFaultBase::invoke(tc, inst); 663#endif |
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656} 657 658void 659SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 660{ | 664} 665 666void 667SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 668{ |
669#if !FULL_SYSTEM |
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661 doNormalFault(tc, trapType(), false); 662 663 Process *p = tc->getProcessPtr(); 664 665 //XXX This will only work in faults from a SparcLiveProcess 666 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 667 assert(lp); 668 669 // Then adjust the PC and NPC 670 tc->pcState(lp->readSpillStart()); | 670 doNormalFault(tc, trapType(), false); 671 672 Process *p = tc->getProcessPtr(); 673 674 //XXX This will only work in faults from a SparcLiveProcess 675 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 676 assert(lp); 677 678 // Then adjust the PC and NPC 679 tc->pcState(lp->readSpillStart()); |
680#else 681 SparcFaultBase::invoke(tc, inst); 682#endif |
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671} 672 673void 674FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 675{ | 683} 684 685void 686FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 687{ |
688#if !FULL_SYSTEM |
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676 doNormalFault(tc, trapType(), false); 677 678 Process *p = tc->getProcessPtr(); 679 680 //XXX This will only work in faults from a SparcLiveProcess 681 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 682 assert(lp); 683 684 // Then adjust the PC and NPC 685 tc->pcState(lp->readFillStart()); | 689 doNormalFault(tc, trapType(), false); 690 691 Process *p = tc->getProcessPtr(); 692 693 //XXX This will only work in faults from a SparcLiveProcess 694 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 695 assert(lp); 696 697 // Then adjust the PC and NPC 698 tc->pcState(lp->readFillStart()); |
699#else 700 SparcFaultBase::invoke(tc, inst); 701#endif |
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686} 687 688void 689TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 690{ | 702} 703 704void 705TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 706{ |
707#if !FULL_SYSTEM |
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691 // In SE, this mechanism is how the process requests a service from the 692 // operating system. We'll get the process object from the thread context 693 // and let it service the request. 694 695 Process *p = tc->getProcessPtr(); 696 697 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 698 assert(lp); 699 700 lp->handleTrap(_n, tc); 701 702 // We need to explicitly advance the pc, since that's not done for us 703 // on a faulting instruction 704 PCState pc = tc->pcState(); 705 pc.advance(); 706 tc->pcState(pc); | 708 // In SE, this mechanism is how the process requests a service from the 709 // operating system. We'll get the process object from the thread context 710 // and let it service the request. 711 712 Process *p = tc->getProcessPtr(); 713 714 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 715 assert(lp); 716 717 lp->handleTrap(_n, tc); 718 719 // We need to explicitly advance the pc, since that's not done for us 720 // on a faulting instruction 721 PCState pc = tc->pcState(); 722 pc.advance(); 723 tc->pcState(pc); |
724#else 725 SparcFaultBase::invoke(tc, inst); 726#endif |
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707} 708 | 727} 728 |
709#endif 710 | |
711} // namespace SparcISA 712 | 729} // namespace SparcISA 730 |