faults.cc (7678:f19b6a3a8cec) | faults.cc (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 293 unchanged lines hidden (view full) --- 302 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 303 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 304 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 305 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 306 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 307 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 308 MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); 309 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 293 unchanged lines hidden (view full) --- 302 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 303 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 304 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 305 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 306 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 307 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 308 MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3); 309 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); |
310 MiscReg PC = tc->readPC(); 311 MiscReg NPC = tc->readNextPC(); | 310 PCState pc = tc->pcState(); |
312 313 TL++; 314 | 311 312 TL++; 313 |
315 if (bits(PSTATE, 3,3)) { 316 PC &= mask(32); 317 NPC &= mask(32); 318 } | 314 Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64); |
319 320 //set TSTATE.gl to gl 321 replaceBits(TSTATE, 42, 40, GL); 322 //set TSTATE.ccr to ccr 323 replaceBits(TSTATE, 39, 32, CCR); 324 //set TSTATE.asi to asi 325 replaceBits(TSTATE, 31, 24, ASI); 326 //set TSTATE.pstate to pstate 327 replaceBits(TSTATE, 20, 8, PSTATE); 328 //set TSTATE.cwp to cwp 329 replaceBits(TSTATE, 4, 0, CWP); 330 331 //Write back TSTATE 332 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 333 334 //set TPC to PC | 315 316 //set TSTATE.gl to gl 317 replaceBits(TSTATE, 42, 40, GL); 318 //set TSTATE.ccr to ccr 319 replaceBits(TSTATE, 39, 32, CCR); 320 //set TSTATE.asi to asi 321 replaceBits(TSTATE, 31, 24, ASI); 322 //set TSTATE.pstate to pstate 323 replaceBits(TSTATE, 20, 8, PSTATE); 324 //set TSTATE.cwp to cwp 325 replaceBits(TSTATE, 4, 0, CWP); 326 327 //Write back TSTATE 328 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 329 330 //set TPC to PC |
335 tc->setMiscRegNoEffect(MISCREG_TPC, PC); | 331 tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); |
336 //set TNPC to NPC | 332 //set TNPC to NPC |
337 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC); | 333 tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); |
338 339 //set HTSTATE.hpstate to hpstate 340 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 341 342 //TT = trap type; 343 tc->setMiscRegNoEffect(MISCREG_TT, tt); 344 345 //Update GL --- 43 unchanged lines hidden (view full) --- 389 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 390 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 391 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 392 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 393 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 394 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 395 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); 396 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); | 334 335 //set HTSTATE.hpstate to hpstate 336 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 337 338 //TT = trap type; 339 tc->setMiscRegNoEffect(MISCREG_TT, tt); 340 341 //Update GL --- 43 unchanged lines hidden (view full) --- 385 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE); 386 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR); 387 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2); 388 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI); 389 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP); 390 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE); 391 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3); 392 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL); |
397 MiscReg PC = tc->readPC(); 398 MiscReg NPC = tc->readNextPC(); | 393 PCState pc = tc->pcState(); |
399 | 394 |
400 if (bits(PSTATE, 3,3)) { 401 PC &= mask(32); 402 NPC &= mask(32); 403 } 404 | |
405 //Increment the trap level 406 TL++; 407 tc->setMiscRegNoEffect(MISCREG_TL, TL); 408 | 395 //Increment the trap level 396 TL++; 397 tc->setMiscRegNoEffect(MISCREG_TL, TL); 398 |
399 Addr pcMask = bits(PSTATE, 3) ? mask(32) : mask(64); 400 |
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409 //Save off state 410 411 //set TSTATE.gl to gl 412 replaceBits(TSTATE, 42, 40, GL); 413 //set TSTATE.ccr to ccr 414 replaceBits(TSTATE, 39, 32, CCR); 415 //set TSTATE.asi to asi 416 replaceBits(TSTATE, 31, 24, ASI); 417 //set TSTATE.pstate to pstate 418 replaceBits(TSTATE, 20, 8, PSTATE); 419 //set TSTATE.cwp to cwp 420 replaceBits(TSTATE, 4, 0, CWP); 421 422 //Write back TSTATE 423 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 424 425 //set TPC to PC | 401 //Save off state 402 403 //set TSTATE.gl to gl 404 replaceBits(TSTATE, 42, 40, GL); 405 //set TSTATE.ccr to ccr 406 replaceBits(TSTATE, 39, 32, CCR); 407 //set TSTATE.asi to asi 408 replaceBits(TSTATE, 31, 24, ASI); 409 //set TSTATE.pstate to pstate 410 replaceBits(TSTATE, 20, 8, PSTATE); 411 //set TSTATE.cwp to cwp 412 replaceBits(TSTATE, 4, 0, CWP); 413 414 //Write back TSTATE 415 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE); 416 417 //set TPC to PC |
426 tc->setMiscRegNoEffect(MISCREG_TPC, PC); | 418 tc->setMiscRegNoEffect(MISCREG_TPC, pc.pc() & pcMask); |
427 //set TNPC to NPC | 419 //set TNPC to NPC |
428 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC); | 420 tc->setMiscRegNoEffect(MISCREG_TNPC, pc.npc() & pcMask); |
429 430 //set HTSTATE.hpstate to hpstate 431 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 432 433 //TT = trap type; 434 tc->setMiscRegNoEffect(MISCREG_TT, tt); 435 436 //Update the global register level --- 37 unchanged lines hidden (view full) --- 474 475 if (changedCWP) 476 { 477 CWP = (CWP + NWindows) % NWindows; 478 tc->setMiscReg(MISCREG_CWP, CWP); 479 } 480} 481 | 421 422 //set HTSTATE.hpstate to hpstate 423 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE); 424 425 //TT = trap type; 426 tc->setMiscRegNoEffect(MISCREG_TT, tt); 427 428 //Update the global register level --- 37 unchanged lines hidden (view full) --- 466 467 if (changedCWP) 468 { 469 CWP = (CWP + NWindows) % NWindows; 470 tc->setMiscReg(MISCREG_CWP, CWP); 471 } 472} 473 |
482void getREDVector(MiscReg TT, Addr & PC, Addr & NPC) | 474void getREDVector(MiscReg TT, Addr &PC, Addr &NPC) |
483{ 484 //XXX The following constant might belong in a header file. 485 const Addr RSTVAddr = 0xFFF0000000ULL; 486 PC = RSTVAddr | ((TT << 5) & 0xFF); 487 NPC = PC + sizeof(MachInst); 488} 489 490void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) --- 58 unchanged lines hidden (view full) --- 549 (level == Privileged && trapType() >= 384)) { 550 doNormalFault(tc, trapType(), true); 551 getHyperVector(tc, PC, NPC, trapType()); 552 } else { 553 doNormalFault(tc, trapType(), false); 554 getPrivVector(tc, PC, NPC, trapType(), tl+1); 555 } 556 | 475{ 476 //XXX The following constant might belong in a header file. 477 const Addr RSTVAddr = 0xFFF0000000ULL; 478 PC = RSTVAddr | ((TT << 5) & 0xFF); 479 NPC = PC + sizeof(MachInst); 480} 481 482void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT) --- 58 unchanged lines hidden (view full) --- 541 (level == Privileged && trapType() >= 384)) { 542 doNormalFault(tc, trapType(), true); 543 getHyperVector(tc, PC, NPC, trapType()); 544 } else { 545 doNormalFault(tc, trapType(), false); 546 getPrivVector(tc, PC, NPC, trapType(), tl+1); 547 } 548 |
557 tc->setPC(PC); 558 tc->setNextPC(NPC); 559 tc->setNextNPC(NPC + sizeof(MachInst)); | 549 PCState pc; 550 pc.pc(PC); 551 pc.npc(NPC); 552 pc.nnpc(NPC + sizeof(MachInst)); 553 pc.upc(0); 554 pc.nupc(1); 555 tc->pcState(pc); |
560} 561 562void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst) 563{ 564 //For SPARC, when a system is first started, there is a power 565 //on reset Trap which sets the processor into the following state. 566 //Bits that aren't set aren't defined on startup. 567 --- 20 unchanged lines hidden (view full) --- 588 tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63); 589 590 //Enter RED state. We do this last so that the actual state preserved in 591 //the trap stack is the state from before this fault. 592 enterREDState(tc); 593 594 Addr PC, NPC; 595 getREDVector(trapType(), PC, NPC); | 556} 557 558void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst) 559{ 560 //For SPARC, when a system is first started, there is a power 561 //on reset Trap which sets the processor into the following state. 562 //Bits that aren't set aren't defined on startup. 563 --- 20 unchanged lines hidden (view full) --- 584 tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63); 585 586 //Enter RED state. We do this last so that the actual state preserved in 587 //the trap stack is the state from before this fault. 588 enterREDState(tc); 589 590 Addr PC, NPC; 591 getREDVector(trapType(), PC, NPC); |
596 tc->setPC(PC); 597 tc->setNextPC(NPC); 598 tc->setNextNPC(NPC + sizeof(MachInst)); | |
599 | 592 |
593 PCState pc; 594 pc.pc(PC); 595 pc.npc(NPC); 596 pc.nnpc(NPC + sizeof(MachInst)); 597 pc.upc(0); 598 pc.nupc(1); 599 tc->pcState(pc); 600 |
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600 //These registers are specified as "undefined" after a POR, and they 601 //should have reasonable values after the miscregfile is reset 602 /* 603 // Clear all the soft interrupt bits 604 softint = 0; 605 // disable timer compare interrupts, reset tick_cmpr 606 tc->setMiscRegNoEffect(MISCREG_ 607 tick_cmprFields.int_dis = 1; --- 51 unchanged lines hidden (view full) --- 659 660 Process *p = tc->getProcessPtr(); 661 662 //XXX This will only work in faults from a SparcLiveProcess 663 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 664 assert(lp); 665 666 //Then adjust the PC and NPC | 601 //These registers are specified as "undefined" after a POR, and they 602 //should have reasonable values after the miscregfile is reset 603 /* 604 // Clear all the soft interrupt bits 605 softint = 0; 606 // disable timer compare interrupts, reset tick_cmpr 607 tc->setMiscRegNoEffect(MISCREG_ 608 tick_cmprFields.int_dis = 1; --- 51 unchanged lines hidden (view full) --- 660 661 Process *p = tc->getProcessPtr(); 662 663 //XXX This will only work in faults from a SparcLiveProcess 664 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 665 assert(lp); 666 667 //Then adjust the PC and NPC |
667 Addr spillStart = lp->readSpillStart(); 668 tc->setPC(spillStart); 669 tc->setNextPC(spillStart + sizeof(MachInst)); 670 tc->setNextNPC(spillStart + 2*sizeof(MachInst)); | 668 tc->pcState(lp->readSpillStart()); |
671} 672 673void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 674{ 675 doNormalFault(tc, trapType(), false); 676 677 Process * p = tc->getProcessPtr(); 678 679 //XXX This will only work in faults from a SparcLiveProcess 680 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 681 assert(lp); 682 683 //Then adjust the PC and NPC | 669} 670 671void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 672{ 673 doNormalFault(tc, trapType(), false); 674 675 Process * p = tc->getProcessPtr(); 676 677 //XXX This will only work in faults from a SparcLiveProcess 678 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 679 assert(lp); 680 681 //Then adjust the PC and NPC |
684 Addr fillStart = lp->readFillStart(); 685 tc->setPC(fillStart); 686 tc->setNextPC(fillStart + sizeof(MachInst)); 687 tc->setNextNPC(fillStart + 2*sizeof(MachInst)); | 682 tc->pcState(lp->readFillStart()); |
688} 689 690void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 691{ 692 //In SE, this mechanism is how the process requests a service from the 693 //operating system. We'll get the process object from the thread context 694 //and let it service the request. 695 696 Process *p = tc->getProcessPtr(); 697 698 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 699 assert(lp); 700 701 lp->handleTrap(_n, tc); 702 703 //We need to explicitly advance the pc, since that's not done for us 704 //on a faulting instruction | 683} 684 685void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 686{ 687 //In SE, this mechanism is how the process requests a service from the 688 //operating system. We'll get the process object from the thread context 689 //and let it service the request. 690 691 Process *p = tc->getProcessPtr(); 692 693 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 694 assert(lp); 695 696 lp->handleTrap(_n, tc); 697 698 //We need to explicitly advance the pc, since that's not done for us 699 //on a faulting instruction |
705 tc->setPC(tc->readNextPC()); 706 tc->setNextPC(tc->readNextNPC()); 707 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst)); | 700 PCState pc = tc->pcState(); 701 pc.advance(); 702 tc->pcState(pc); |
708} 709 710#endif 711 712} // namespace SparcISA 713 | 703} 704 705#endif 706 707} // namespace SparcISA 708 |