faults.cc (4183:3d19c1d46946) faults.cc (4997:e7380529bd2d)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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615 hintp = 0; // no interrupts pending
616 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
617 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
618 */
619}
620
621#else // !FULL_SYSTEM
622
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 606 unchanged lines hidden (view full) ---

615 hintp = 0; // no interrupts pending
616 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
617 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
618 */
619}
620
621#else // !FULL_SYSTEM
622
623void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
624{
625 Process *p = tc->getProcessPtr();
626 Addr paddr;
627 bool success = p->pTable->translate(vaddr, paddr);
628 if(!success) {
629 panic("Tried to execute unmapped address %#x.\n", vaddr);
630 } else {
631
632 uint64_t entry = 0;
633 entry |= 0ULL << 1; // Not writable
634 entry |= 0ULL << 2; // Available in nonpriveleged mode
635 entry |= 0ULL << 3; // No side effects
636 entry |= 1ULL << 4; // Virtually cachable
637 entry |= 1ULL << 5; // Physically cachable
638 entry |= 0ULL << 6; // Not locked
639 entry |= mbits(paddr, 39, 13); // Physical address
640 entry |= 0ULL << 48; // size = 8k
641 entry |= 0uLL << 59; // Endianness not inverted
642 entry |= 0ULL << 60; // Not no fault only
643 entry |= 0ULL << 61; // size = 8k
644 entry |= 1ULL << 63; // valid
645 PageTableEntry PTE(entry);
646
647 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
648 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
649 p->M5_pid /*context id*/, false, PTE);
650 }
651}
652
653void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
654{
655 Process *p = tc->getProcessPtr();
656 Addr paddr;
657 bool success = p->pTable->translate(vaddr, paddr);
658 if(!success) {
659 p->checkAndAllocNextPage(vaddr);
660 success = p->pTable->translate(vaddr, paddr);
661 }
662 if(!success) {
663 panic("Tried to access unmapped address %#x.\n", vaddr);
664 } else {
665
666 uint64_t entry = 0;
667 entry |= 1ULL << 1; // Writable
668 entry |= 0ULL << 2; // Available in nonpriveleged mode
669 entry |= 0ULL << 3; // No side effects
670 entry |= 1ULL << 4; // Virtually cachable
671 entry |= 1ULL << 5; // Physically cachable
672 entry |= 0ULL << 6; // Not locked
673 entry |= mbits(paddr, 39, 13); // Physical address
674 entry |= 0ULL << 48; // size = 8k
675 entry |= 0uLL << 59; // Endianness not inverted
676 entry |= 0ULL << 60; // Not no fault only
677 entry |= 0ULL << 61; // size = 8k
678 entry |= 1ULL << 63; // valid
679 PageTableEntry PTE(entry);
680
681 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
682 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
683 p->M5_pid /*context id*/, false, PTE);
684 }
685}
686
623void SpillNNormal::invoke(ThreadContext *tc)
624{
625 doNormalFault(tc, trapType(), false);
626
627 Process *p = tc->getProcessPtr();
628
629 //XXX This will only work in faults from a SparcLiveProcess
630 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);

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687void SpillNNormal::invoke(ThreadContext *tc)
688{
689 doNormalFault(tc, trapType(), false);
690
691 Process *p = tc->getProcessPtr();
692
693 //XXX This will only work in faults from a SparcLiveProcess
694 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);

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