faults.cc (3746:c55a63fb4cf3) faults.cc (3761:b7c7f547d5a3)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301 MiscReg TL = tc->readMiscReg(MISCREG_TL);
302 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301 MiscReg TL = tc->readMiscReg(MISCREG_TL);
302 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
305 //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
306 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
307 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
307 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
308 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
308 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
309 //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
310 MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
309 MiscReg GL = tc->readMiscReg(MISCREG_GL);
310 MiscReg PC = tc->readPC();
311 MiscReg NPC = tc->readNextPC();
312
313 TL++;
314
315 //set TSTATE.gl to gl
316 replaceBits(TSTATE, 42, 40, GL);

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391 */
392
393void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
394{
395 MiscReg TL = tc->readMiscReg(MISCREG_TL);
396 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
397 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
398 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
311 MiscReg GL = tc->readMiscReg(MISCREG_GL);
312 MiscReg PC = tc->readPC();
313 MiscReg NPC = tc->readNextPC();
314
315 TL++;
316
317 //set TSTATE.gl to gl
318 replaceBits(TSTATE, 42, 40, GL);

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393 */
394
395void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
396{
397 MiscReg TL = tc->readMiscReg(MISCREG_TL);
398 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
399 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
400 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
399 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
401 //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
402 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
400 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
401 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
403 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
404 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
402 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
405 //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
406 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
403 MiscReg GL = tc->readMiscReg(MISCREG_GL);
404 MiscReg PC = tc->readPC();
405 MiscReg NPC = tc->readNextPC();
406
407 //Increment the trap level
408 TL++;
409 tc->setMiscReg(MISCREG_TL, TL);
410

--- 298 unchanged lines hidden --- 		407 MiscReg GL = tc->readMiscReg(MISCREG_GL);
408 MiscReg PC = tc->readPC();
409 MiscReg NPC = tc->readNextPC();
410
411 //Increment the trap level
412 TL++;
413 tc->setMiscReg(MISCREG_TL, TL);
414

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