faults.cc (3628:b562d6fc3893) | faults.cc (3746:c55a63fb4cf3) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 270 unchanged lines hidden (view full) --- 279 //@todo Disable the mmu? 280 //@todo Disable watchpoints? 281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 282 //HPSTATE.red = 1 283 HPSTATE |= (1 << 5); 284 //HPSTATE.hpriv = 1 285 HPSTATE |= (1 << 2); 286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE); | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 270 unchanged lines hidden (view full) --- 279 //@todo Disable the mmu? 280 //@todo Disable watchpoints? 281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 282 //HPSTATE.red = 1 283 HPSTATE |= (1 << 5); 284 //HPSTATE.hpriv = 1 285 HPSTATE |= (1 << 2); 286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE); |
287 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 288 //Legion sets it to 1. 289 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 290 PSTATE |= (1 << 2); 291 tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE); |
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287} 288 289/** 290 * This sets everything up for a RED state trap except for actually jumping to 291 * the handler. 292 */ 293 294void doREDFault(ThreadContext *tc, TrapType tt) --- 40 unchanged lines hidden (view full) --- 335 //Update GL 336 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); 337 338 //set PSTATE.mm to 00 339 //set PSTATE.pef to 1 340 PSTATE |= (1 << 4); 341 //set PSTATE.am to 0 342 PSTATE &= ~(1 << 3); | 292} 293 294/** 295 * This sets everything up for a RED state trap except for actually jumping to 296 * the handler. 297 */ 298 299void doREDFault(ThreadContext *tc, TrapType tt) --- 40 unchanged lines hidden (view full) --- 340 //Update GL 341 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL)); 342 343 //set PSTATE.mm to 00 344 //set PSTATE.pef to 1 345 PSTATE |= (1 << 4); 346 //set PSTATE.am to 0 347 PSTATE &= ~(1 << 3); |
343 //set PSTATE.priv to 0 344 PSTATE &= ~(1 << 2); | 348/* //set PSTATE.priv to 0 349 PSTATE &= ~(1 << 2);*/ |
345 //set PSTATE.ie to 0 | 350 //set PSTATE.ie to 0 |
346 PSTATE &= ~(1 << 1); | 351 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 352 //Legion sets it to 1. 353 PSTATE |= (1 << 2); |
347 //set PSTATE.cle to 0 348 PSTATE &= ~(1 << 9); 349 //PSTATE.tle is unchanged 350 //XXX Where is the tct bit? 351 //set PSTATE.tct to 0 352 tc->setMiscReg(MISCREG_PSTATE, PSTATE); 353 354 //set HPSTATE.red to 1 --- 91 unchanged lines hidden (view full) --- 446 //PSTATE.priv = 1 447 PSTATE |= (1 << 2); 448 //PSTATE.cle = PSTATE.tle 449 replaceBits(PSTATE, 9, 9, PSTATE >> 8); 450 } 451 else 452 { 453 //PSTATE.priv = 0 | 354 //set PSTATE.cle to 0 355 PSTATE &= ~(1 << 9); 356 //PSTATE.tle is unchanged 357 //XXX Where is the tct bit? 358 //set PSTATE.tct to 0 359 tc->setMiscReg(MISCREG_PSTATE, PSTATE); 360 361 //set HPSTATE.red to 1 --- 91 unchanged lines hidden (view full) --- 453 //PSTATE.priv = 1 454 PSTATE |= (1 << 2); 455 //PSTATE.cle = PSTATE.tle 456 replaceBits(PSTATE, 9, 9, PSTATE >> 8); 457 } 458 else 459 { 460 //PSTATE.priv = 0 |
454 PSTATE &= ~(1 << 2); | 461 //PSTATE.priv is set to 1 here. The manual says it should be 0, but 462 //Legion sets it to 1. 463 PSTATE |= (1 << 2); |
455 //PSTATE.cle = 0 456 PSTATE &= ~(1 << 9); 457 } 458 //PSTATE.ie = 0 459 PSTATE &= ~(1 << 1); 460 //PSTATE.tle is unchanged 461 //PSTATE.tct = 0 462 //XXX Where exactly is this field? --- 65 unchanged lines hidden (view full) --- 528 MiscReg TL = tc->readMiscReg(MISCREG_TL); 529 MiscReg TT = tc->readMiscReg(MISCREG_TT); 530 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 531 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 532 533 Addr PC, NPC; 534 535 PrivilegeLevel current; | 464 //PSTATE.cle = 0 465 PSTATE &= ~(1 << 9); 466 } 467 //PSTATE.ie = 0 468 PSTATE &= ~(1 << 1); 469 //PSTATE.tle is unchanged 470 //PSTATE.tct = 0 471 //XXX Where exactly is this field? --- 65 unchanged lines hidden (view full) --- 537 MiscReg TL = tc->readMiscReg(MISCREG_TL); 538 MiscReg TT = tc->readMiscReg(MISCREG_TT); 539 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE); 540 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 541 542 Addr PC, NPC; 543 544 PrivilegeLevel current; |
536 if(!(PSTATE & (1 << 2))) 537 current = User; 538 else if(!(HPSTATE & (1 << 2))) | 545 if(HPSTATE & (1 << 2)) 546 current = Hyperprivileged; 547 else if(PSTATE & (1 << 2)) |
539 current = Privileged; 540 else | 548 current = Privileged; 549 else |
541 current = Hyperprivileged; | 550 current = User; |
542 543 PrivilegeLevel level = getNextLevel(current); 544 545 if(HPSTATE & (1 << 5) || TL == MaxTL - 1) 546 { 547 getREDVector(5, PC, NPC); | 551 552 PrivilegeLevel level = getNextLevel(current); 553 554 if(HPSTATE & (1 << 5) || TL == MaxTL - 1) 555 { 556 getREDVector(5, PC, NPC); |
548 enterREDState(tc); | |
549 doREDFault(tc, TT); | 557 doREDFault(tc, TT); |
558 //This changes the hpstate and pstate, so we need to make sure we 559 //save the old version on the trap stack in doREDFault. 560 enterREDState(tc); |
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550 } 551 else if(TL == MaxTL) 552 { 553 //Do error_state somehow? 554 //Probably inject a WDR fault using the interrupt mechanism. 555 //What should the PC and NPC be set to? 556 } 557 else if(TL > MaxPTL && level == Privileged) --- 15 unchanged lines hidden (view full) --- 573 574 tc->setPC(PC); 575 tc->setNextPC(NPC); 576 tc->setNextNPC(NPC + sizeof(MachInst)); 577} 578 579void PowerOnReset::invoke(ThreadContext * tc) 580{ | 561 } 562 else if(TL == MaxTL) 563 { 564 //Do error_state somehow? 565 //Probably inject a WDR fault using the interrupt mechanism. 566 //What should the PC and NPC be set to? 567 } 568 else if(TL > MaxPTL && level == Privileged) --- 15 unchanged lines hidden (view full) --- 584 585 tc->setPC(PC); 586 tc->setNextPC(NPC); 587 tc->setNextNPC(NPC + sizeof(MachInst)); 588} 589 590void PowerOnReset::invoke(ThreadContext * tc) 591{ |
581 //First, enter RED state. 582 enterREDState(tc); 583 | |
584 //For SPARC, when a system is first started, there is a power 585 //on reset Trap which sets the processor into the following state. 586 //Bits that aren't set aren't defined on startup. 587 588 tc->setMiscReg(MISCREG_TL, MaxTL); 589 tc->setMiscReg(MISCREG_TT, trapType()); 590 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL); 591 | 592 //For SPARC, when a system is first started, there is a power 593 //on reset Trap which sets the processor into the following state. 594 //Bits that aren't set aren't defined on startup. 595 596 tc->setMiscReg(MISCREG_TL, MaxTL); 597 tc->setMiscReg(MISCREG_TT, trapType()); 598 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL); 599 |
592 //Turn on pef, set everything else to 0 593 tc->setMiscReg(MISCREG_PSTATE, 1 << 4); | 600 //Turn on pef and priv, set everything else to 0 601 tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2)); |
594 595 //Turn on red and hpriv, set everything else to 0 596 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 597 //HPSTATE.red = 1 598 HPSTATE |= (1 << 5); 599 //HPSTATE.hpriv = 1 600 HPSTATE |= (1 << 2); 601 //HPSTATE.ibe = 0 602 HPSTATE &= ~(1 << 10); 603 //HPSTATE.tlz = 0 604 HPSTATE &= ~(1 << 0); 605 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 606 607 //The tick register is unreadable by nonprivileged software 608 tc->setMiscReg(MISCREG_TICK, 1ULL << 63); 609 | 602 603 //Turn on red and hpriv, set everything else to 0 604 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE); 605 //HPSTATE.red = 1 606 HPSTATE |= (1 << 5); 607 //HPSTATE.hpriv = 1 608 HPSTATE |= (1 << 2); 609 //HPSTATE.ibe = 0 610 HPSTATE &= ~(1 << 10); 611 //HPSTATE.tlz = 0 612 HPSTATE &= ~(1 << 0); 613 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE); 614 615 //The tick register is unreadable by nonprivileged software 616 tc->setMiscReg(MISCREG_TICK, 1ULL << 63); 617 |
618 //Enter RED state. We do this last so that the actual state preserved in 619 //the trap stack is the state from before this fault. 620 enterREDState(tc); 621 |
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610 Addr PC, NPC; 611 getREDVector(trapType(), PC, NPC); 612 tc->setPC(PC); 613 tc->setNextPC(NPC); 614 tc->setNextNPC(NPC + sizeof(MachInst)); 615 616 //These registers are specified as "undefined" after a POR, and they 617 //should have reasonable values after the miscregfile is reset --- 79 unchanged lines hidden --- | 622 Addr PC, NPC; 623 getREDVector(trapType(), PC, NPC); 624 tc->setPC(PC); 625 tc->setNextPC(NPC); 626 tc->setNextNPC(NPC + sizeof(MachInst)); 627 628 //These registers are specified as "undefined" after a POR, and they 629 //should have reasonable values after the miscregfile is reset --- 79 unchanged lines hidden --- |