faults.cc (3585:774b5b26a51a) faults.cc (3595:71574f980a5d)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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278{
279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282 //HPSTATE.red = 1
283 HPSTATE |= (1 << 5);
284 //HPSTATE.hpriv = 1
285 HPSTATE |= (1 << 2);
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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278{
279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282 //HPSTATE.red = 1
283 HPSTATE |= (1 << 5);
284 //HPSTATE.hpriv = 1
285 HPSTATE |= (1 << 2);
286 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287}
288
289/**
290 * This sets everything up for a RED state trap except for actually jumping to
291 * the handler.
292 */
293
294void doREDFault(ThreadContext *tc, TrapType tt)

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486
487 if(changedCWP)
488 {
489 CWP = (CWP + NWindows) % NWindows;
490 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
491 }
492}
493
287}
288
289/**
290 * This sets everything up for a RED state trap except for actually jumping to
291 * the handler.
292 */
293
294void doREDFault(ThreadContext *tc, TrapType tt)

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486
487 if(changedCWP)
488 {
489 CWP = (CWP + NWindows) % NWindows;
490 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
491 }
492}
493
494void getREDVector(Addr & PC, Addr & NPC)
494void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
495{
496 //XXX The following constant might belong in a header file.
497 const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
495{
496 //XXX The following constant might belong in a header file.
497 const Addr RSTVAddr = 0xFFFFFFFFF0000000ULL;
498 PC = RSTVAddr | 0xA0;
498 PC = RSTVAddr | ((TT << 5) & 0xFF);
499 NPC = PC + sizeof(MachInst);
500}
501
502void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
503{
504 Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
505 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
506 NPC = PC + sizeof(MachInst);

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514 ((TT << 5) & mask(14));
515 NPC = PC + sizeof(MachInst);
516}
517
518#if FULL_SYSTEM
519
520void SparcFaultBase::invoke(ThreadContext * tc)
521{
499 NPC = PC + sizeof(MachInst);
500}
501
502void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
503{
504 Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
505 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
506 NPC = PC + sizeof(MachInst);

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514 ((TT << 5) & mask(14));
515 NPC = PC + sizeof(MachInst);
516}
517
518#if FULL_SYSTEM
519
520void SparcFaultBase::invoke(ThreadContext * tc)
521{
522 panic("Invoking a second fault!\n");
522 FaultBase::invoke(tc);
523 countStat()++;
524
525 //We can refer to this to see what the trap level -was-, but something
526 //in the middle could change it in the regfile out from under us.
527 MiscReg TL = tc->readMiscReg(MISCREG_TL);
528 MiscReg TT = tc->readMiscReg(MISCREG_TT);
529 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);

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538 current = Privileged;
539 else
540 current = Hyperprivileged;
541
542 PrivilegeLevel level = getNextLevel(current);
543
544 if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
545 {
523 FaultBase::invoke(tc);
524 countStat()++;
525
526 //We can refer to this to see what the trap level -was-, but something
527 //in the middle could change it in the regfile out from under us.
528 MiscReg TL = tc->readMiscReg(MISCREG_TL);
529 MiscReg TT = tc->readMiscReg(MISCREG_TT);
530 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);

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539 current = Privileged;
540 else
541 current = Hyperprivileged;
542
543 PrivilegeLevel level = getNextLevel(current);
544
545 if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
546 {
546 getREDVector(PC, NPC);
547 getREDVector(5, PC, NPC);
547 enterREDState(tc);
548 doREDFault(tc, TT);
549 }
550 else if(TL == MaxTL)
551 {
552 //Do error_state somehow?
553 //Probably inject a WDR fault using the interrupt mechanism.
554 //What should the PC and NPC be set to?

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578void PowerOnReset::invoke(ThreadContext * tc)
579{
580 //First, enter RED state.
581 enterREDState(tc);
582
583 //For SPARC, when a system is first started, there is a power
584 //on reset Trap which sets the processor into the following state.
585 //Bits that aren't set aren't defined on startup.
548 enterREDState(tc);
549 doREDFault(tc, TT);
550 }
551 else if(TL == MaxTL)
552 {
553 //Do error_state somehow?
554 //Probably inject a WDR fault using the interrupt mechanism.
555 //What should the PC and NPC be set to?

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579void PowerOnReset::invoke(ThreadContext * tc)
580{
581 //First, enter RED state.
582 enterREDState(tc);
583
584 //For SPARC, when a system is first started, there is a power
585 //on reset Trap which sets the processor into the following state.
586 //Bits that aren't set aren't defined on startup.
586 /*
587 tl = MaxTL;
588 gl = MaxGL;
589
587
590 tickFields.counter = 0; //The TICK register is unreadable bya
591 tickFields.npt = 1; //The TICK register is unreadable by by !priv
588 tc->setMiscReg(MISCREG_TL, MaxTL);
589 tc->setMiscReg(MISCREG_TT, trapType());
590 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
592
591
593 softint = 0; // Clear all the soft interrupt bits
594 tick_cmprFields.int_dis = 1; // disable timer compare interrupts
592 //Turn on pef, set everything else to 0
593 tc->setMiscReg(MISCREG_PSTATE, 1 << 4);
594
595 //Turn on red and hpriv, set everything else to 0
596 tc->setMiscReg(MISCREG_HPSTATE, (1 << 5) | (1 << 2));
597
598 //The tick register is unreadable by nonprivileged software
599 tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
600
601 Addr PC, NPC;
602 getREDVector(trapType(), PC, NPC);
603 tc->setPC(PC);
604 tc->setNextPC(NPC);
605 tc->setNextNPC(NPC + sizeof(MachInst));
606
607 //These registers are specified as "undefined" after a POR, and they
608 //should have reasonable values after the miscregfile is reset
609 /*
610 // Clear all the soft interrupt bits
611 softint = 0;
612 // disable timer compare interrupts, reset tick_cmpr
613 tc->setMiscReg(MISCREG_
614 tick_cmprFields.int_dis = 1;
595 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
596 stickFields.npt = 1; //The TICK register is unreadable by by !priv
597 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
598 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
599
600 tt[tl] = _trapType;
615 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
616 stickFields.npt = 1; //The TICK register is unreadable by by !priv
617 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
618 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
619
620 tt[tl] = _trapType;
601 pstate = 0; // fields 0 but pef
602 pstateFields.pef = 1;
603
621
604 hpstate = 0;
605 hpstateFields.red = 1;
606 hpstateFields.hpriv = 1;
607 hpstateFields.tlz = 0; // this is a guess
608 hintp = 0; // no interrupts pending
609 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
610 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
611 */
612}
613
614#else // !FULL_SYSTEM
615

--- 58 unchanged lines hidden --- 		622 hintp = 0; // no interrupts pending
623 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
624 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
625 */
626}
627
628#else // !FULL_SYSTEM
629

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