faults.cc (3574:dbddfe6ebb2d) faults.cc (3576:c5a2b916a9fa)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45#endif
46
47using namespace std;
48
49namespace SparcISA
50{
51
52template<> SparcFaultBase::FaultVals
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 36 unchanged lines hidden (view full) ---

45#endif
46
47using namespace std;
48
49namespace SparcISA
50{
51
52template<> SparcFaultBase::FaultVals
53 SparcFault<InternalProcessorError>::vals = {"intprocerr", 0x029, 4};
53 SparcFault<PowerOnReset>::vals =
54 {"power_on_reset", 0x001, 0, {H, H, H}};
54
55template<> SparcFaultBase::FaultVals
55
56template<> SparcFaultBase::FaultVals
56 SparcFault<MemAddressNotAligned>::vals = {"unalign", 0x034, 10};
57 SparcFault<WatchDogReset>::vals =
58 {"watch_dog_reset", 0x002, 120, {H, H, H}};
57
58template<> SparcFaultBase::FaultVals
59
60template<> SparcFaultBase::FaultVals
59 SparcFault<PowerOnReset>::vals = {"pow_reset", 0x001, 0};
61 SparcFault<ExternallyInitiatedReset>::vals =
62 {"externally_initiated_reset", 0x003, 110, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
63
64template<> SparcFaultBase::FaultVals
62 SparcFault<WatchDogReset>::vals = {"watch_dog_reset", 0x002, 1};
65 SparcFault<SoftwareInitiatedReset>::vals =
66 {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
63
64template<> SparcFaultBase::FaultVals
67
68template<> SparcFaultBase::FaultVals
65 SparcFault<ExternallyInitiatedReset>::vals = {"extern_reset", 0x003, 1};
69 SparcFault<REDStateException>::vals =
70 {"RED_state_exception", 0x005, 1, {H, H, H}};
66
67template<> SparcFaultBase::FaultVals
71
72template<> SparcFaultBase::FaultVals
68 SparcFault<SoftwareInitiatedReset>::vals = {"software_reset", 0x004, 1};
73 SparcFault<StoreError>::vals =
74 {"store_error", 0x007, 201, {H, H, H}};
69
70template<> SparcFaultBase::FaultVals
75
76template<> SparcFaultBase::FaultVals
71 SparcFault<REDStateException>::vals = {"red_counte", 0x005, 1};
77 SparcFault<InstructionAccessException>::vals =
78 {"instruction_access_exception", 0x008, 300, {H, H, H}};
72
79
80//XXX This trap is apparently dropped from ua2005
81/*template<> SparcFaultBase::FaultVals
82 SparcFault<InstructionAccessMMUMiss>::vals =
83 {"inst_mmu", 0x009, 2, {H, H, H}};*/
84
73template<> SparcFaultBase::FaultVals
85template<> SparcFaultBase::FaultVals
74 SparcFault<InstructionAccessException>::vals = {"inst_access", 0x008, 5};
86 SparcFault<InstructionAccessError>::vals =
87 {"instruction_access_error", 0x00A, 400, {H, H, H}};
75
76template<> SparcFaultBase::FaultVals
88
89template<> SparcFaultBase::FaultVals
77 SparcFault<InstructionAccessMMUMiss>::vals = {"inst_mmu", 0x009, 2};
90 SparcFault<IllegalInstruction>::vals =
91 {"illegal_instruction", 0x010, 620, {H, H, H}};
78
79template<> SparcFaultBase::FaultVals
92
93template<> SparcFaultBase::FaultVals
80 SparcFault<InstructionAccessError>::vals = {"inst_error", 0x00A, 3};
94 SparcFault<PrivilegedOpcode>::vals =
95 {"privileged_opcode", 0x011, 700, {P, SH, SH}};
81
96
97//XXX This trap is apparently dropped from ua2005
98/*template<> SparcFaultBase::FaultVals
99 SparcFault<UnimplementedLDD>::vals =
100 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
101
102//XXX This trap is apparently dropped from ua2005
103/*template<> SparcFaultBase::FaultVals
104 SparcFault<UnimplementedSTD>::vals =
105 {"unimp_std", 0x013, 6, {H, H, H}};*/
106
82template<> SparcFaultBase::FaultVals
107template<> SparcFaultBase::FaultVals
83 SparcFault<IllegalInstruction>::vals = {"illegal_inst", 0x010, 7};
108 SparcFault<FpDisabled>::vals =
109 {"fp_disabled", 0x020, 800, {P, P, H}};
84
85template<> SparcFaultBase::FaultVals
110
111template<> SparcFaultBase::FaultVals
86 SparcFault<PrivilegedOpcode>::vals = {"priv_opcode", 0x011, 6};
112 SparcFault<FpExceptionIEEE754>::vals =
113 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
87
88template<> SparcFaultBase::FaultVals
114
115template<> SparcFaultBase::FaultVals
89 SparcFault<UnimplementedLDD>::vals = {"unimp_ldd", 0x012, 6};
116 SparcFault<FpExceptionOther>::vals =
117 {"fp_exception_other", 0x022, 1110, {P, P, H}};
90
91template<> SparcFaultBase::FaultVals
118
119template<> SparcFaultBase::FaultVals
92 SparcFault<UnimplementedSTD>::vals = {"unimp_std", 0x013, 6};
120 SparcFault<TagOverflow>::vals =
121 {"tag_overflow", 0x023, 1400, {P, P, H}};
93
94template<> SparcFaultBase::FaultVals
122
123template<> SparcFaultBase::FaultVals
95 SparcFault<FpDisabled>::vals = {"fp_disabled", 0x020, 8};
124 SparcFault<CleanWindow>::vals =
125 {"clean_window", 0x024, 1010, {P, P, H}};
96
97template<> SparcFaultBase::FaultVals
126
127template<> SparcFaultBase::FaultVals
98 SparcFault<FpExceptionIEEE754>::vals = {"fp_754", 0x021, 11};
128 SparcFault<DivisionByZero>::vals =
129 {"division_by_zero", 0x028, 1500, {P, P, H}};
99
100template<> SparcFaultBase::FaultVals
130
131template<> SparcFaultBase::FaultVals
101 SparcFault<FpExceptionOther>::vals = {"fp_other", 0x022, 11};
132 SparcFault<InternalProcessorError>::vals =
133 {"internal_processor_error", 0x029, 4, {H, H, H}};
102
103template<> SparcFaultBase::FaultVals
134
135template<> SparcFaultBase::FaultVals
104 SparcFault<TagOverflow>::vals = {"tag_overflow", 0x023, 14};
136 SparcFault<InstructionInvalidTSBEntry>::vals =
137 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
105
106template<> SparcFaultBase::FaultVals
138
139template<> SparcFaultBase::FaultVals
107 SparcFault<DivisionByZero>::vals = {"div_by_zero", 0x028, 15};
140 SparcFault<DataInvalidTSBEntry>::vals =
141 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
108
109template<> SparcFaultBase::FaultVals
142
143template<> SparcFaultBase::FaultVals
110 SparcFault<DataAccessException>::vals = {"data_access", 0x030, 12};
144 SparcFault::vals =
145 {"data_access_exception", 0x030, 1201, {H, H, H}};
111
146
147//XXX This trap is apparently dropped from ua2005
148/*template<> SparcFaultBase::FaultVals
149 SparcFault<DataAccessMMUMiss>::vals =
150 {"data_mmu", 0x031, 12, {H, H, H}};*/
151
112template<> SparcFaultBase::FaultVals
152template<> SparcFaultBase::FaultVals
113 SparcFault<DataAccessMMUMiss>::vals = {"data_mmu", 0x031, 12};
153 SparcFault<DataAccessError>::vals =
154 {"data_access_error", 0x032, 1210, {H, H, H}};
114
115template<> SparcFaultBase::FaultVals
155
156template<> SparcFaultBase::FaultVals
116 SparcFault<DataAccessError>::vals = {"data_error", 0x032, 12};
157 SparcFault<DataAccessProtection>::vals =
158 {"data_access_protection", 0x033, 1207, {H, H, H}};
117
118template<> SparcFaultBase::FaultVals
159
160template<> SparcFaultBase::FaultVals
119 SparcFault<DataAccessProtection>::vals = {"data_protection", 0x033, 12};
161 SparcFault<MemAddressNotAligned>::vals =
162 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
120
121template<> SparcFaultBase::FaultVals
163
164template<> SparcFaultBase::FaultVals
122 SparcFault<LDDFMemAddressNotAligned>::vals = {"unalign_lddf", 0x035, 10};
165 SparcFault::vals =
166 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
123
124template<> SparcFaultBase::FaultVals
167
168template<> SparcFaultBase::FaultVals
125 SparcFault<STDFMemAddressNotAligned>::vals = {"unalign_stdf", 0x036, 10};
169 SparcFault::vals =
170 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
126
127template<> SparcFaultBase::FaultVals
171
172template<> SparcFaultBase::FaultVals
128 SparcFault<PrivilegedAction>::vals = {"priv_action", 0x037, 11};
173 SparcFault::vals =
174 {"privileged_action", 0x037, 1110, {H, H, SH}};
129
130template<> SparcFaultBase::FaultVals
175
176template<> SparcFaultBase::FaultVals
131 SparcFault<LDQFMemAddressNotAligned>::vals = {"unalign_ldqf", 0x038, 10};
177 SparcFault::vals =
178 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
132
133template<> SparcFaultBase::FaultVals
179
180template<> SparcFaultBase::FaultVals
134 SparcFault<STQFMemAddressNotAligned>::vals = {"unalign_stqf", 0x039, 10};
181 SparcFault::vals =
182 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
183
184template<> SparcFaultBase::FaultVals
137 SparcFault<AsyncDataError>::vals = {"async_data", 0x040, 2};
185 SparcFault<InstructionRealTranslationMiss>::vals =
186 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
138
139template<> SparcFaultBase::FaultVals
187
188template<> SparcFaultBase::FaultVals
140 SparcFault<CleanWindow>::vals = {"clean_win", 0x024, 10};
189 SparcFault<DataRealTranslationMiss>::vals =
190 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
141
191
142//The enumerated faults
192//XXX This trap is apparently dropped from ua2005
193/*template<> SparcFaultBase::FaultVals
194 SparcFault<AsyncDataError>::vals =
195 {"async_data", 0x040, 2, {H, H, H}};*/
143
144template<> SparcFaultBase::FaultVals
196
197template<> SparcFaultBase::FaultVals
145 SparcFault<InterruptLevelN>::vals = {"interrupt_n", 0x041, 0};
198 SparcFault::vals =
199 {"interrupt_level_n", 0x041, 0, {P, P, SH}};
146
147template<> SparcFaultBase::FaultVals
200
201template<> SparcFaultBase::FaultVals
148 SparcFault<SpillNNormal>::vals = {"spill_n_normal", 0x080, 9};
202 SparcFault<HstickMatch>::vals =
203 {"hstick_match", 0x05E, 1601, {H, H, H}};
149
150template<> SparcFaultBase::FaultVals
204
205template<> SparcFaultBase::FaultVals
151 SparcFault<SpillNOther>::vals = {"spill_n_other", 0x0A0, 9};
206 SparcFault<TrapLevelZero>::vals =
207 {"trap_level_zero", 0x05F, 202, {H, H, SH}};
152
153template<> SparcFaultBase::FaultVals
208
209template<> SparcFaultBase::FaultVals
154 SparcFault<FillNNormal>::vals = {"fill_n_normal", 0x0C0, 9};
210 SparcFault<PAWatchpoint>::vals =
211 {"PA_watchpoint", 0x061, 1209, {H, H, H}};
155
156template<> SparcFaultBase::FaultVals
212
213template<> SparcFaultBase::FaultVals
157 SparcFault<FillNOther>::vals = {"fill_n_other", 0x0E0, 9};
214 SparcFault<VAWatchpoint>::vals =
215 {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
158
159template<> SparcFaultBase::FaultVals
216
217template<> SparcFaultBase::FaultVals
160 SparcFault<TrapInstruction>::vals = {"trap_inst_n", 0x100, 16};
218 SparcFault<FastInstructionAccessMMUMiss>::vals =
219 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
161
220
221template<> SparcFaultBase::FaultVals
222 SparcFault<FastDataAccessMMUMiss>::vals =
223 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
224
225template<> SparcFaultBase::FaultVals
226 SparcFault<FastDataAccessProtection>::vals =
227 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
228
229template<> SparcFaultBase::FaultVals
230 SparcFault<InstructionBreakpoint>::vals =
231 {"instruction_break", 0x076, 610, {H, H, H}};
232
233template<> SparcFaultBase::FaultVals
234 SparcFault<CpuMondo>::vals =
235 {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
236
237template<> SparcFaultBase::FaultVals
238 SparcFault<DevMondo>::vals =
239 {"dev_mondo", 0x07D, 1611, {P, P, SH}};
240
241template<> SparcFaultBase::FaultVals
242 SparcFault<ResumeableError>::vals =
243 {"resume_error", 0x07E, 3330, {P, P, SH}};
244
245template<> SparcFaultBase::FaultVals
246 SparcFault<SpillNNormal>::vals =
247 {"spill_n_normal", 0x080, 900, {P, P, H}};
248
249template<> SparcFaultBase::FaultVals
250 SparcFault<SpillNOther>::vals =
251 {"spill_n_other", 0x0A0, 900, {P, P, H}};
252
253template<> SparcFaultBase::FaultVals
254 SparcFault<FillNNormal>::vals =
255 {"fill_n_normal", 0x0C0, 900, {P, P, H}};
256
257template<> SparcFaultBase::FaultVals
258 SparcFault<FillNOther>::vals =
259 {"fill_n_other", 0x0E0, 900, {P, P, H}};
260
261template<> SparcFaultBase::FaultVals
262 SparcFault<TrapInstruction>::vals =
263 {"trap_instruction", 0x100, 1602, {P, P, H}};
264
162#if !FULL_SYSTEM
163template<> SparcFaultBase::FaultVals
265#if !FULL_SYSTEM
266template<> SparcFaultBase::FaultVals
164 SparcFault<PageTableFault>::vals = {"page_table_fault", 0x0000, 0};
267 SparcFault::vals =
268 {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
165#endif
166
167/**
168 * This sets everything up for a normal trap except for actually jumping to
169 * the handler. It will need to be expanded to include the state machine in
170 * the manual. Right now it assumes that traps will always be to the
171 * privileged level.
172 */

--- 214 unchanged lines hidden --- 		269#endif
270
271/**
272 * This sets everything up for a normal trap except for actually jumping to
273 * the handler. It will need to be expanded to include the state machine in
274 * the manual. Right now it assumes that traps will always be to the
275 * privileged level.
276 */

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