faults.cc (3455:fdc8b63937ca) faults.cc (3523:f145bc050815)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/process.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#if !FULL_SYSTEM
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#if !FULL_SYSTEM
42#include "arch/sparc/process.hh"
42#include "mem/page_table.hh"
43#include "sim/process.hh"
44#endif
45
46using namespace std;
47
48namespace SparcISA
49{

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356void SparcFault::invoke(ThreadContext * tc)
357{
358 FaultBase::invoke(tc);
359 countStat()++;
360
361 //Use the SPARC trap state machine
362}
363
43#include "mem/page_table.hh"
44#include "sim/process.hh"
45#endif
46
47using namespace std;
48
49namespace SparcISA
50{

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357void SparcFault::invoke(ThreadContext * tc)
358{
359 FaultBase::invoke(tc);
360 countStat()++;
361
362 //Use the SPARC trap state machine
363}
364
365void PowerOnReset::invoke(ThreadContext * tc)
366{
367 //For SPARC, when a system is first started, there is a power
368 //on reset Trap which sets the processor into the following state.
369 //Bits that aren't set aren't defined on startup.
370 /*
371 tl = MaxTL;
372 gl = MaxGL;
373
374 tickFields.counter = 0; //The TICK register is unreadable bya
375 tickFields.npt = 1; //The TICK register is unreadable by by !priv
376
377 softint = 0; // Clear all the soft interrupt bits
378 tick_cmprFields.int_dis = 1; // disable timer compare interrupts
379 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
380 stickFields.npt = 1; //The TICK register is unreadable by by !priv
381 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
382 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
383
384 tt[tl] = _trapType;
385 pstate = 0; // fields 0 but pef
386 pstateFields.pef = 1;
387
388 hpstate = 0;
389 hpstateFields.red = 1;
390 hpstateFields.hpriv = 1;
391 hpstateFields.tlz = 0; // this is a guess
392 hintp = 0; // no interrupts pending
393 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
394 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
395 */
396}
397
364#endif
365
366#if !FULL_SYSTEM
367
368void TrapInstruction::invoke(ThreadContext * tc)
369{
370 // Should be handled in ISA.
371}

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399
400#if !FULL_SYSTEM
401
402void TrapInstruction::invoke(ThreadContext * tc)
403{
404 // Should be handled in ISA.
405}

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