faults.cc (3420:839edd067438) faults.cc (3455:fdc8b63937ca)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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354#if FULL_SYSTEM
355
356void SparcFault::invoke(ThreadContext * tc)
357{
358 FaultBase::invoke(tc);
359 countStat()++;
360
361 //Use the SPARC trap state machine
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 345 unchanged lines hidden (view full) ---

354#if FULL_SYSTEM
355
356void SparcFault::invoke(ThreadContext * tc)
357{
358 FaultBase::invoke(tc);
359 countStat()++;
360
361 //Use the SPARC trap state machine
362 /*// exception restart address
363 if (setRestartAddress() || !tc->inPalMode())
364 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
365
366 if (skipFaultingInstruction()) {
367 // traps... skip faulting instruction.
368 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
369 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
370 }
371
372 if (!tc->inPalMode())
373 AlphaISA::swap_palshadow(&(tc->regs), true);
374
375 tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
376 tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
377}
378
379#endif
380
381#if !FULL_SYSTEM
382
383void TrapInstruction::invoke(ThreadContext * tc)
384{

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363
364#endif
365
366#if !FULL_SYSTEM
367
368void TrapInstruction::invoke(ThreadContext * tc)
369{

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