faults.cc (3415:72c48f292f6a) faults.cc (3420:839edd067438)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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331 //HPSTATE.ibe = 0
332 HPSTATE &= ~(1 << 10);
333 //HPSTATE.tlz is unchanged
334 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
335 }
336
337 bool changedCWP = true;
338 if(tt == 0x24)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 322 unchanged lines hidden (view full) ---

331 //HPSTATE.ibe = 0
332 HPSTATE &= ~(1 << 10);
333 //HPSTATE.tlz is unchanged
334 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
335 }
336
337 bool changedCWP = true;
338 if(tt == 0x24)
339 {
340 warn("Incrementing the CWP by 1\n");
341 CWP++;
339 CWP++;
342 }
343 else if(0x80 <= tt && tt <= 0xbf)
340 else if(0x80 <= tt && tt <= 0xbf)
344 {
345 warn("Incrementing the CWP by %d\n", CANSAVE + 2);
346 CWP += (CANSAVE + 2);
341 CWP += (CANSAVE + 2);
347 }
348 else if(0xc0 <= tt && tt <= 0xff)
342 else if(0xc0 <= tt && tt <= 0xff)
349 {
350 warn("Decrementing the CWP by 1\n");
351 CWP--;
343 CWP--;
352 }
353 else
354 changedCWP = false;
344 else
345 changedCWP = false;
346
355 if(changedCWP)
356 {
357 CWP = (CWP + NWindows) % NWindows;
358 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
359 }
360}
361
362#if FULL_SYSTEM

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390
391void TrapInstruction::invoke(ThreadContext * tc)
392{
393 // Should be handled in ISA.
394}
395
396void SpillNNormal::invoke(ThreadContext *tc)
397{
347 if(changedCWP)
348 {
349 CWP = (CWP + NWindows) % NWindows;
350 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
351 }
352}
353
354#if FULL_SYSTEM

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382
383void TrapInstruction::invoke(ThreadContext * tc)
384{
385 // Should be handled in ISA.
386}
387
388void SpillNNormal::invoke(ThreadContext *tc)
389{
398 warn("I'm in a spill trap\n");
399 doNormalFault(tc, trapType());
400
401 Process *p = tc->getProcessPtr();
402
403 //This will only work in faults from a SparcLiveProcess
404 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
405 assert(lp);
406
407 //Then adjust the PC and NPC
408 Addr spillStart = lp->readSpillStart();
409 tc->setPC(spillStart);
410 tc->setNextPC(spillStart + sizeof(MachInst));
411 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
412}
413
414void FillNNormal::invoke(ThreadContext *tc)
415{
390 doNormalFault(tc, trapType());
391
392 Process *p = tc->getProcessPtr();
393
394 //This will only work in faults from a SparcLiveProcess
395 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
396 assert(lp);
397
398 //Then adjust the PC and NPC
399 Addr spillStart = lp->readSpillStart();
400 tc->setPC(spillStart);
401 tc->setNextPC(spillStart + sizeof(MachInst));
402 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
403}
404
405void FillNNormal::invoke(ThreadContext *tc)
406{
416 warn("I'm in a fill trap\n");
417 doNormalFault(tc, trapType());
418
419 Process * p = tc->getProcessPtr();
420
421 //This will only work in faults from a SparcLiveProcess
422 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
423 assert(lp);
424

--- 31 unchanged lines hidden --- 		407 doNormalFault(tc, trapType());
408
409 Process * p = tc->getProcessPtr();
410
411 //This will only work in faults from a SparcLiveProcess
412 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
413 assert(lp);
414

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