faults.cc (2665:a124942bacb8) faults.cc (2680:246e7104f744)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/sparc/faults.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 16 unchanged lines hidden (view full) ---

25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include "arch/sparc/faults.hh"
33#include "cpu/exec_context.hh"
33#include "cpu/thread_context.hh"
34#include "cpu/base.hh"
35#include "base/trace.hh"
36
37namespace SparcISA
38{
39
40FaultName InternalProcessorError::_name = "intprocerr";
41TrapType InternalProcessorError::_trapType = 0x029;

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215
216FaultName TrapInstruction::_name = "trap_inst_n";
217TrapType TrapInstruction::_baseTrapType = 0x100;
218FaultPriority TrapInstruction::_priority = 16;
219FaultStat TrapInstruction::_count;
220
221#if FULL_SYSTEM
222
34#include "cpu/base.hh"
35#include "base/trace.hh"
36
37namespace SparcISA
38{
39
40FaultName InternalProcessorError::_name = "intprocerr";
41TrapType InternalProcessorError::_trapType = 0x029;

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215
216FaultName TrapInstruction::_name = "trap_inst_n";
217TrapType TrapInstruction::_baseTrapType = 0x100;
218FaultPriority TrapInstruction::_priority = 16;
219FaultStat TrapInstruction::_count;
220
221#if FULL_SYSTEM
222
223void SparcFault::invoke(ExecContext * xc)
223void SparcFault::invoke(ThreadContext * tc)
224{
224{
225 FaultBase::invoke(xc);
225 FaultBase::invoke(tc);
226 countStat()++;
227
228 //Use the SPARC trap state machine
229 /*// exception restart address
226 countStat()++;
227
228 //Use the SPARC trap state machine
229 /*// exception restart address
230 if (setRestartAddress() || !xc->inPalMode())
231 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
230 if (setRestartAddress() || !tc->inPalMode())
231 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
232
233 if (skipFaultingInstruction()) {
234 // traps... skip faulting instruction.
232
233 if (skipFaultingInstruction()) {
234 // traps... skip faulting instruction.
235 xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
236 xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
235 tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
236 tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
237 }
238
237 }
238
239 if (!xc->inPalMode())
240 AlphaISA::swap_palshadow(&(xc->regs), true);
239 if (!tc->inPalMode())
240 AlphaISA::swap_palshadow(&(tc->regs), true);
241
241
242 xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
243 xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
242 tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
243 tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
244}
245
246#endif
247
248#if !FULL_SYSTEM
249
244}
245
246#endif
247
248#if !FULL_SYSTEM
249
250void TrapInstruction::invoke(ExecContext * xc)
250void TrapInstruction::invoke(ThreadContext * tc)
251{
251{
252 xc->syscall(syscall_num);
252 tc->syscall(syscall_num);
253}
254
255#endif
256
257} // namespace SparcISA
258
253}
254
255#endif
256
257} // namespace SparcISA
258