faults.cc (12572:749b07984c79) faults.cc (13583:f7482392b097)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 288 unchanged lines hidden (view full) ---

297/**
298 * This sets everything up for a RED state trap except for actually jumping to
299 * the handler.
300 */
301
302void
303doREDFault(ThreadContext *tc, TrapType tt)
304{
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 288 unchanged lines hidden (view full) ---

297/**
298 * This sets everything up for a RED state trap except for actually jumping to
299 * the handler.
300 */
301
302void
303doREDFault(ThreadContext *tc, TrapType tt)
304{
305 MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
306 MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
305 RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
306 RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
307 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
307 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
309 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
310 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
311 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
312 MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
313 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
309 RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
310 RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
311 RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
312 RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
313 RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
314 PCState pc = tc->pcState();
315
316 TL++;
317
318 Addr pcMask = pstate.am ? mask(32) : mask(64);
319
320 // set TSTATE.gl to gl
321 replaceBits(TSTATE, 42, 40, GL);

--- 54 unchanged lines hidden (view full) ---

376/**
377 * This sets everything up for a normal trap except for actually jumping to
378 * the handler.
379 */
380
381void
382doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
383{
314 PCState pc = tc->pcState();
315
316 TL++;
317
318 Addr pcMask = pstate.am ? mask(32) : mask(64);
319
320 // set TSTATE.gl to gl
321 replaceBits(TSTATE, 42, 40, GL);

--- 54 unchanged lines hidden (view full) ---

376/**
377 * This sets everything up for a normal trap except for actually jumping to
378 * the handler.
379 */
380
381void
382doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
383{
384 MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
385 MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
384 RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
385 RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
386 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
387 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
386 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
387 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
388 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
389 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
390 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
391 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
392 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
388 RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
389 RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
390 RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
391 RegVal CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
392 RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
393 PCState pc = tc->pcState();
394
395 // Increment the trap level
396 TL++;
397 tc->setMiscRegNoEffect(MISCREG_TL, TL);
398
399 Addr pcMask = pstate.am ? mask(32) : mask(64);
400

--- 64 unchanged lines hidden (view full) ---

465
466 if (changedCWP) {
467 CWP = (CWP + NWindows) % NWindows;
468 tc->setMiscReg(MISCREG_CWP, CWP);
469 }
470}
471
472void
393 PCState pc = tc->pcState();
394
395 // Increment the trap level
396 TL++;
397 tc->setMiscRegNoEffect(MISCREG_TL, TL);
398
399 Addr pcMask = pstate.am ? mask(32) : mask(64);
400

--- 64 unchanged lines hidden (view full) ---

465
466 if (changedCWP) {
467 CWP = (CWP + NWindows) % NWindows;
468 tc->setMiscReg(MISCREG_CWP, CWP);
469 }
470}
471
472void
473getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
473getREDVector(RegVal TT, Addr &PC, Addr &NPC)
474{
475 //XXX The following constant might belong in a header file.
476 const Addr RSTVAddr = 0xFFF0000000ULL;
477 PC = RSTVAddr | ((TT << 5) & 0xFF);
478 NPC = PC + sizeof(MachInst);
479}
480
481void
474{
475 //XXX The following constant might belong in a header file.
476 const Addr RSTVAddr = 0xFFF0000000ULL;
477 PC = RSTVAddr | ((TT << 5) & 0xFF);
478 NPC = PC + sizeof(MachInst);
479}
480
481void
482getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
482getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT)
483{
484 Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
485 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
486 NPC = PC + sizeof(MachInst);
487}
488
489void
483{
484 Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
485 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
486 NPC = PC + sizeof(MachInst);
487}
488
489void
490getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
490getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
491{
492 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
493 PC = (TBA & ~mask(15)) |
494 (TL > 1 ? (1 << 14) : 0) |
495 ((TT << 5) & mask(14));
496 NPC = PC + sizeof(MachInst);
497}
498
499void
500SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
501{
502 FaultBase::invoke(tc);
503 if (!FullSystem)
504 return;
505
506 countStat()++;
507
508 // We can refer to this to see what the trap level -was-, but something
509 // in the middle could change it in the regfile out from under us.
491{
492 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
493 PC = (TBA & ~mask(15)) |
494 (TL > 1 ? (1 << 14) : 0) |
495 ((TT << 5) & mask(14));
496 NPC = PC + sizeof(MachInst);
497}
498
499void
500SparcFaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst)
501{
502 FaultBase::invoke(tc);
503 if (!FullSystem)
504 return;
505
506 countStat()++;
507
508 // We can refer to this to see what the trap level -was-, but something
509 // in the middle could change it in the regfile out from under us.
510 MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
511 MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
510 RegVal tl = tc->readMiscRegNoEffect(MISCREG_TL);
511 RegVal tt = tc->readMiscRegNoEffect(MISCREG_TT);
512 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
513 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
514
515 Addr PC, NPC;
516
517 PrivilegeLevel current;
518 if (hpstate.hpriv)
519 current = Hyperprivileged;

--- 206 unchanged lines hidden (view full) ---

726 // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
727 // MISCREG_ASI causes me to think that the ASI register implementation
728 // might be bugged. The NoEffect variant changes the ASI register
729 // value in the architectural state while the normal variant changes
730 // the context field in the thread context's currently decoded request
731 // but does not directly affect the ASI register value in the
732 // architectural state. The ASI values and the context field in the
733 // request packet seem to have completely different uses.
512 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
513 HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
514
515 Addr PC, NPC;
516
517 PrivilegeLevel current;
518 if (hpstate.hpriv)
519 current = Hyperprivileged;

--- 206 unchanged lines hidden (view full) ---

726 // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
727 // MISCREG_ASI causes me to think that the ASI register implementation
728 // might be bugged. The NoEffect variant changes the ASI register
729 // value in the architectural state while the normal variant changes
730 // the context field in the thread context's currently decoded request
731 // but does not directly affect the ASI register value in the
732 // architectural state. The ASI values and the context field in the
733 // request packet seem to have completely different uses.
734 MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
734 RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
735 ASI asi = static_cast<ASI>(reg_asi);
736
737 // The SPARC DTLB code assumes that traps are executed in context
738 // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
739 // an assumption that the nucleus address space is being used, but
740 // the context is the relevant issue since we need to pass it to TLB.
741 bool trapped = bits(tlbdata, 18, 16) > 0;
742

--- 90 unchanged lines hidden --- 		735 ASI asi = static_cast<ASI>(reg_asi);
736
737 // The SPARC DTLB code assumes that traps are executed in context
738 // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
739 // an assumption that the nucleus address space is being used, but
740 // the context is the relevant issue since we need to pass it to TLB.
741 bool trapped = bits(tlbdata, 18, 16) > 0;
742

--- 90 unchanged lines hidden ---