faults.cc (12517:77e8688fc670) faults.cc (12572:749b07984c79)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 38 unchanged lines hidden (view full) ---

47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals
55("power_on_reset", 0x001, 0, {H, H, H});
55("power_on_reset", 0x001, 0, {{H, H, H}});
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals
59("watch_dog_reset", 0x002, 120, {H, H, H});
59("watch_dog_reset", 0x002, 120, {{H, H, H}});
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals
63("externally_initiated_reset", 0x003, 110, {H, H, H});
63("externally_initiated_reset", 0x003, 110, {{H, H, H}});
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals
67("software_initiated_reset", 0x004, 130, {SH, SH, H});
67("software_initiated_reset", 0x004, 130, {{SH, SH, H}});
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals
71("RED_state_exception", 0x005, 1, {H, H, H});
71("RED_state_exception", 0x005, 1, {{H, H, H}});
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals
75("store_error", 0x007, 201, {H, H, H});
75("store_error", 0x007, 201, {{H, H, H}});
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals
79("instruction_access_exception", 0x008, 300, {H, H, H});
79("instruction_access_exception", 0x008, 300, {{H, H, H}});
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
84 ("inst_mmu", 0x009, 2, {{H, H, H}});*/
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals
88("instruction_access_error", 0x00A, 400, {H, H, H});
88("instruction_access_error", 0x00A, 400, {{H, H, H}});
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals
92("illegal_instruction", 0x010, 620, {H, H, H});
92("illegal_instruction", 0x010, 620, {{H, H, H}});
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals
96("privileged_opcode", 0x011, 700, {P, SH, SH});
96("privileged_opcode", 0x011, 700, {{P, SH, SH}});
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
101 ("unimp_ldd", 0x012, 6, {{H, H, H}});*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
106 ("unimp_std", 0x013, 6, {{H, H, H}});*/
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals
110("fp_disabled", 0x020, 800, {P, P, H});
110("fp_disabled", 0x020, 800, {{P, P, H}});
111
112/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
113 * as a separate part. Therefore, we use the same code and TT */
114template<> SparcFaultBase::FaultVals
111
112/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
113 * as a separate part. Therefore, we use the same code and TT */
114template<> SparcFaultBase::FaultVals
115 SparcFault<VecDisabled>::vals =
116{"fp_disabled", 0x020, 800, {P, P, H}};
115 SparcFault::vals
116("fp_disabled", 0x020, 800, {{P, P, H}});
117
118template<> SparcFaultBase::FaultVals
119 SparcFault<FpExceptionIEEE754>::vals
117
118template<> SparcFaultBase::FaultVals
119 SparcFault<FpExceptionIEEE754>::vals
120("fp_exception_ieee_754", 0x021, 1110, {P, P, H});
120("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}});
121
122template<> SparcFaultBase::FaultVals
123 SparcFault<FpExceptionOther>::vals
121
122template<> SparcFaultBase::FaultVals
123 SparcFault<FpExceptionOther>::vals
124("fp_exception_other", 0x022, 1110, {P, P, H});
124("fp_exception_other", 0x022, 1110, {{P, P, H}});
125
126template<> SparcFaultBase::FaultVals
127 SparcFault<TagOverflow>::vals
125
126template<> SparcFaultBase::FaultVals
127 SparcFault<TagOverflow>::vals
128("tag_overflow", 0x023, 1400, {P, P, H});
128("tag_overflow", 0x023, 1400, {{P, P, H}});
129
130template<> SparcFaultBase::FaultVals
131 SparcFault<CleanWindow>::vals
129
130template<> SparcFaultBase::FaultVals
131 SparcFault<CleanWindow>::vals
132("clean_window", 0x024, 1010, {P, P, H});
132("clean_window", 0x024, 1010, {{P, P, H}});
133
134template<> SparcFaultBase::FaultVals
135 SparcFault<DivisionByZero>::vals
133
134template<> SparcFaultBase::FaultVals
135 SparcFault<DivisionByZero>::vals
136("division_by_zero", 0x028, 1500, {P, P, H});
136("division_by_zero", 0x028, 1500, {{P, P, H}});
137
138template<> SparcFaultBase::FaultVals
139 SparcFault<InternalProcessorError>::vals
137
138template<> SparcFaultBase::FaultVals
139 SparcFault<InternalProcessorError>::vals
140("internal_processor_error", 0x029, 4, {H, H, H});
140("internal_processor_error", 0x029, 4, {{H, H, H}});
141
142template<> SparcFaultBase::FaultVals
143 SparcFault<InstructionInvalidTSBEntry>::vals
141
142template<> SparcFaultBase::FaultVals
143 SparcFault<InstructionInvalidTSBEntry>::vals
144("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH});
144("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}});
145
146template<> SparcFaultBase::FaultVals
147 SparcFault<DataInvalidTSBEntry>::vals
145
146template<> SparcFaultBase::FaultVals
147 SparcFault<DataInvalidTSBEntry>::vals
148("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H});
148("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}});
149
150template<> SparcFaultBase::FaultVals
151 SparcFault<DataAccessException>::vals
149
150template<> SparcFaultBase::FaultVals
151 SparcFault<DataAccessException>::vals
152("data_access_exception", 0x030, 1201, {H, H, H});
152("data_access_exception", 0x030, 1201, {{H, H, H}});
153
154//XXX This trap is apparently dropped from ua2005
155/*template<> SparcFaultBase::FaultVals
156 SparcFault<DataAccessMMUMiss>::vals
153
154//XXX This trap is apparently dropped from ua2005
155/*template<> SparcFaultBase::FaultVals
156 SparcFault<DataAccessMMUMiss>::vals
157 {"data_mmu", 0x031, 12, {H, H, H}};*/
157 ("data_mmu", 0x031, 12, {{H, H, H}});*/
158
159template<> SparcFaultBase::FaultVals
160 SparcFault<DataAccessError>::vals
158
159template<> SparcFaultBase::FaultVals
160 SparcFault<DataAccessError>::vals
161("data_access_error", 0x032, 1210, {H, H, H});
161("data_access_error", 0x032, 1210, {{H, H, H}});
162
163template<> SparcFaultBase::FaultVals
164 SparcFault<DataAccessProtection>::vals
162
163template<> SparcFaultBase::FaultVals
164 SparcFault<DataAccessProtection>::vals
165("data_access_protection", 0x033, 1207, {H, H, H});
165("data_access_protection", 0x033, 1207, {{H, H, H}});
166
167template<> SparcFaultBase::FaultVals
168 SparcFault<MemAddressNotAligned>::vals
166
167template<> SparcFaultBase::FaultVals
168 SparcFault<MemAddressNotAligned>::vals
169("mem_address_not_aligned", 0x034, 1020, {H, H, H});
169("mem_address_not_aligned", 0x034, 1020, {{H, H, H}});
170
171template<> SparcFaultBase::FaultVals
172 SparcFault<LDDFMemAddressNotAligned>::vals
170
171template<> SparcFaultBase::FaultVals
172 SparcFault<LDDFMemAddressNotAligned>::vals
173("LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H});
173("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}});
174
175template<> SparcFaultBase::FaultVals
176 SparcFault<STDFMemAddressNotAligned>::vals
174
175template<> SparcFaultBase::FaultVals
176 SparcFault<STDFMemAddressNotAligned>::vals
177("STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H});
177("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}});
178
179template<> SparcFaultBase::FaultVals
180 SparcFault<PrivilegedAction>::vals
178
179template<> SparcFaultBase::FaultVals
180 SparcFault<PrivilegedAction>::vals
181("privileged_action", 0x037, 1110, {H, H, SH});
181("privileged_action", 0x037, 1110, {{H, H, SH}});
182
183template<> SparcFaultBase::FaultVals
184 SparcFault<LDQFMemAddressNotAligned>::vals
182
183template<> SparcFaultBase::FaultVals
184 SparcFault<LDQFMemAddressNotAligned>::vals
185("LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H});
185("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}});
186
187template<> SparcFaultBase::FaultVals
188 SparcFault<STQFMemAddressNotAligned>::vals
186
187template<> SparcFaultBase::FaultVals
188 SparcFault<STQFMemAddressNotAligned>::vals
189("STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H});
189("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}});
190
191template<> SparcFaultBase::FaultVals
192 SparcFault<InstructionRealTranslationMiss>::vals
190
191template<> SparcFaultBase::FaultVals
192 SparcFault<InstructionRealTranslationMiss>::vals
193("instruction_real_translation_miss", 0x03E, 208, {H, H, SH});
193("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}});
194
195template<> SparcFaultBase::FaultVals
196 SparcFault<DataRealTranslationMiss>::vals
194
195template<> SparcFaultBase::FaultVals
196 SparcFault<DataRealTranslationMiss>::vals
197("data_real_translation_miss", 0x03F, 1203, {H, H, H});
197("data_real_translation_miss", 0x03F, 1203, {{H, H, H}});
198
199//XXX This trap is apparently dropped from ua2005
200/*template<> SparcFaultBase::FaultVals
201 SparcFault<AsyncDataError>::vals
198
199//XXX This trap is apparently dropped from ua2005
200/*template<> SparcFaultBase::FaultVals
201 SparcFault<AsyncDataError>::vals
202 {"async_data", 0x040, 2, {H, H, H}};*/
202 ("async_data", 0x040, 2, {{H, H, H}});*/
203
204template<> SparcFaultBase::FaultVals
205 SparcFault<InterruptLevelN>::vals
203
204template<> SparcFaultBase::FaultVals
205 SparcFault<InterruptLevelN>::vals
206("interrupt_level_n", 0x040, 0, {P, P, SH});
206("interrupt_level_n", 0x040, 0, {{P, P, SH}});
207
208template<> SparcFaultBase::FaultVals
209 SparcFault<HstickMatch>::vals
207
208template<> SparcFaultBase::FaultVals
209 SparcFault<HstickMatch>::vals
210("hstick_match", 0x05E, 1601, {H, H, H});
210("hstick_match", 0x05E, 1601, {{H, H, H}});
211
212template<> SparcFaultBase::FaultVals
213 SparcFault<TrapLevelZero>::vals
211
212template<> SparcFaultBase::FaultVals
213 SparcFault<TrapLevelZero>::vals
214("trap_level_zero", 0x05F, 202, {H, H, SH});
214("trap_level_zero", 0x05F, 202, {{H, H, SH}});
215
216template<> SparcFaultBase::FaultVals
217 SparcFault<InterruptVector>::vals
215
216template<> SparcFaultBase::FaultVals
217 SparcFault<InterruptVector>::vals
218("interrupt_vector", 0x060, 2630, {H, H, H});
218("interrupt_vector", 0x060, 2630, {{H, H, H}});
219
220template<> SparcFaultBase::FaultVals
221 SparcFault<PAWatchpoint>::vals
219
220template<> SparcFaultBase::FaultVals
221 SparcFault<PAWatchpoint>::vals
222("PA_watchpoint", 0x061, 1209, {H, H, H});
222("PA_watchpoint", 0x061, 1209, {{H, H, H}});
223
224template<> SparcFaultBase::FaultVals
225 SparcFault<VAWatchpoint>::vals
223
224template<> SparcFaultBase::FaultVals
225 SparcFault<VAWatchpoint>::vals
226("VA_watchpoint", 0x062, 1120, {P, P, SH});
226("VA_watchpoint", 0x062, 1120, {{P, P, SH}});
227
228template<> SparcFaultBase::FaultVals
229 SparcFault<FastInstructionAccessMMUMiss>::vals
227
228template<> SparcFaultBase::FaultVals
229 SparcFault<FastInstructionAccessMMUMiss>::vals
230("fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH});
230("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}});
231
232template<> SparcFaultBase::FaultVals
233 SparcFault<FastDataAccessMMUMiss>::vals
231
232template<> SparcFaultBase::FaultVals
233 SparcFault<FastDataAccessMMUMiss>::vals
234("fast_data_access_MMU_miss", 0x068, 1203, {H, H, H});
234("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}});
235
236template<> SparcFaultBase::FaultVals
237 SparcFault<FastDataAccessProtection>::vals
235
236template<> SparcFaultBase::FaultVals
237 SparcFault<FastDataAccessProtection>::vals
238("fast_data_access_protection", 0x06C, 1207, {H, H, H});
238("fast_data_access_protection", 0x06C, 1207, {{H, H, H}});
239
240template<> SparcFaultBase::FaultVals
241 SparcFault<InstructionBreakpoint>::vals
239
240template<> SparcFaultBase::FaultVals
241 SparcFault<InstructionBreakpoint>::vals
242("instruction_break", 0x076, 610, {H, H, H});
242("instruction_break", 0x076, 610, {{H, H, H}});
243
244template<> SparcFaultBase::FaultVals
245 SparcFault<CpuMondo>::vals
243
244template<> SparcFaultBase::FaultVals
245 SparcFault<CpuMondo>::vals
246("cpu_mondo", 0x07C, 1608, {P, P, SH});
246("cpu_mondo", 0x07C, 1608, {{P, P, SH}});
247
248template<> SparcFaultBase::FaultVals
249 SparcFault<DevMondo>::vals
247
248template<> SparcFaultBase::FaultVals
249 SparcFault<DevMondo>::vals
250("dev_mondo", 0x07D, 1611, {P, P, SH});
250("dev_mondo", 0x07D, 1611, {{P, P, SH}});
251
252template<> SparcFaultBase::FaultVals
253 SparcFault<ResumableError>::vals
251
252template<> SparcFaultBase::FaultVals
253 SparcFault<ResumableError>::vals
254("resume_error", 0x07E, 3330, {P, P, SH});
254("resume_error", 0x07E, 3330, {{P, P, SH}});
255
256template<> SparcFaultBase::FaultVals
257 SparcFault<SpillNNormal>::vals
255
256template<> SparcFaultBase::FaultVals
257 SparcFault<SpillNNormal>::vals
258("spill_n_normal", 0x080, 900, {P, P, H});
258("spill_n_normal", 0x080, 900, {{P, P, H}});
259
260template<> SparcFaultBase::FaultVals
261 SparcFault<SpillNOther>::vals
259
260template<> SparcFaultBase::FaultVals
261 SparcFault<SpillNOther>::vals
262("spill_n_other", 0x0A0, 900, {P, P, H});
262("spill_n_other", 0x0A0, 900, {{P, P, H}});
263
264template<> SparcFaultBase::FaultVals
265 SparcFault<FillNNormal>::vals
263
264template<> SparcFaultBase::FaultVals
265 SparcFault<FillNNormal>::vals
266("fill_n_normal", 0x0C0, 900, {P, P, H});
266("fill_n_normal", 0x0C0, 900, {{P, P, H}});
267
268template<> SparcFaultBase::FaultVals
269 SparcFault<FillNOther>::vals
267
268template<> SparcFaultBase::FaultVals
269 SparcFault<FillNOther>::vals
270("fill_n_other", 0x0E0, 900, {P, P, H});
270("fill_n_other", 0x0E0, 900, {{P, P, H}});
271
272template<> SparcFaultBase::FaultVals
273 SparcFault<TrapInstruction>::vals
271
272template<> SparcFaultBase::FaultVals
273 SparcFault<TrapInstruction>::vals
274("trap_instruction", 0x100, 1602, {P, P, H});
274("trap_instruction", 0x100, 1602, {{P, P, H}});
275
276/**
277 * This causes the thread context to enter RED state. This causes the side
278 * effects which go with entering RED state because of a trap.
279 */
280
281void
282enterREDState(ThreadContext *tc)

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276/**
277 * This causes the thread context to enter RED state. This causes the side
278 * effects which go with entering RED state because of a trap.
279 */
280
281void
282enterREDState(ThreadContext *tc)

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