faults.cc (12455:c88f0b37f433) faults.cc (12461:a4cb506cda74)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#include "arch/sparc/faults.hh"
33
34#include <algorithm>
35
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/process.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#include "arch/sparc/faults.hh"
33
34#include <algorithm>
35
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/process.hh"
38#include "arch/sparc/tlb.hh"
38#include "arch/sparc/types.hh"
39#include "base/bitfield.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "mem/page_table.hh"
44#include "sim/full_system.hh"
45#include "sim/process.hh"

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624 const StaticInstPtr &inst)
625{
626 if (FullSystem) {
627 SparcFaultBase::invoke(tc, inst);
628 return;
629 }
630
631 Process *p = tc->getProcessPtr();
39#include "arch/sparc/types.hh"
40#include "base/bitfield.hh"
41#include "base/trace.hh"
42#include "cpu/base.hh"
43#include "cpu/thread_context.hh"
44#include "mem/page_table.hh"
45#include "sim/full_system.hh"
46#include "sim/process.hh"

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625 const StaticInstPtr &inst)
626{
627 if (FullSystem) {
628 SparcFaultBase::invoke(tc, inst);
629 return;
630 }
631
632 Process *p = tc->getProcessPtr();
632 TlbEntry *entry = p->pTable->lookup(vaddr);
633 panic_if(!entry, "Tried to execute unmapped address %#x.\n", vaddr);
633 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
634 panic_if(!pte, "Tried to execute unmapped address %#x.\n", vaddr);
634
635 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
636
637 // Grab fields used during instruction translation to figure out
638 // which context to use.
639 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
640
641 // Inside a VM, a real address is the address that guest OS would

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657
658 // The partition id distinguishes between virtualized environments.
659 int const partition_id = 0;
660
661 // Given the assumptions in the translateInst code in the SPARC ITLB,
662 // the logic works out to the following for the context.
663 int context_id = (is_real_address || trapped) ? 0 : primary_context;
664
635
636 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
637
638 // Grab fields used during instruction translation to figure out
639 // which context to use.
640 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
641
642 // Inside a VM, a real address is the address that guest OS would

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658
659 // The partition id distinguishes between virtualized environments.
660 int const partition_id = 0;
661
662 // Given the assumptions in the translateInst code in the SPARC ITLB,
663 // the logic works out to the following for the context.
664 int context_id = (is_real_address || trapped) ? 0 : primary_context;
665
666 TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
667 pte->flags & EmulationPageTable::Uncacheable,
668 pte->flags & EmulationPageTable::ReadOnly);
669
665 // Insert the TLB entry.
666 // The entry specifying whether the address is "real" is set to
667 // false for syscall emulation mode regardless of whether the
668 // address is real in preceding code. Not sure sure that this is
669 // correct, but also not sure if it matters at all.
670 dynamic_cast<TLB *>(tc->getITBPtr())->
670 // Insert the TLB entry.
671 // The entry specifying whether the address is "real" is set to
672 // false for syscall emulation mode regardless of whether the
673 // address is real in preceding code. Not sure sure that this is
674 // correct, but also not sure if it matters at all.
675 dynamic_cast<TLB *>(tc->getITBPtr())->
671 insert(alignedvaddr, partition_id, context_id, false, entry->pte);
676 insert(alignedvaddr, partition_id, context_id, false, entry.pte);
672}
673
674void
675FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
676{
677 if (FullSystem) {
678 SparcFaultBase::invoke(tc, inst);
679 return;
680 }
681
682 Process *p = tc->getProcessPtr();
677}
678
679void
680FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
681{
682 if (FullSystem) {
683 SparcFaultBase::invoke(tc, inst);
684 return;
685 }
686
687 Process *p = tc->getProcessPtr();
683 TlbEntry *entry = p->pTable->lookup(vaddr);
684 if (!entry && p->fixupStackFault(vaddr))
685 entry = p->pTable->lookup(vaddr);
686 panic_if(!entry, "Tried to access unmapped address %#x.\n", vaddr);
688 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
689 if (!pte && p->fixupStackFault(vaddr))
690 pte = p->pTable->lookup(vaddr);
691 panic_if(!pte, "Tried to access unmapped address %#x.\n", vaddr);
687
688 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
689
690 // Grab fields used during data translation to figure out
691 // which context to use.
692 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
693
694 // The primary context acts as a PASID. It allows the MMU to

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740 int context_id = ((!hpriv && !red && is_real_address) ||
741 asiIsReal(asi) ||
742 (trapped && asi == ASI_IMPLICIT))
743 ? 0 : primary_context;
744
745 // The partition id distinguishes between virtualized environments.
746 int const partition_id = 0;
747
692
693 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
694
695 // Grab fields used during data translation to figure out
696 // which context to use.
697 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
698
699 // The primary context acts as a PASID. It allows the MMU to

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745 int context_id = ((!hpriv && !red && is_real_address) ||
746 asiIsReal(asi) ||
747 (trapped && asi == ASI_IMPLICIT))
748 ? 0 : primary_context;
749
750 // The partition id distinguishes between virtualized environments.
751 int const partition_id = 0;
752
753 TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr,
754 pte->flags & EmulationPageTable::Uncacheable,
755 pte->flags & EmulationPageTable::ReadOnly);
756
748 // Insert the TLB entry.
749 // The entry specifying whether the address is "real" is set to
750 // false for syscall emulation mode regardless of whether the
751 // address is real in preceding code. Not sure sure that this is
752 // correct, but also not sure if it matters at all.
753 dynamic_cast<TLB *>(tc->getDTBPtr())->
757 // Insert the TLB entry.
758 // The entry specifying whether the address is "real" is set to
759 // false for syscall emulation mode regardless of whether the
760 // address is real in preceding code. Not sure sure that this is
761 // correct, but also not sure if it matters at all.
762 dynamic_cast<TLB *>(tc->getDTBPtr())->
754 insert(alignedvaddr, partition_id, context_id, false, entry->pte);
763 insert(alignedvaddr, partition_id, context_id, false, entry.pte);
755}
756
757void
758SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
759{
760 if (FullSystem) {
761 SparcFaultBase::invoke(tc, inst);
762 return;

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765
766void
767SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
768{
769 if (FullSystem) {
770 SparcFaultBase::invoke(tc, inst);
771 return;

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