faults.cc (12110:c24ee249b8ba) faults.cc (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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664 // the logic works out to the following for the context.
665 int context_id = (is_real_address || trapped) ? 0 : primary_context;
666
667 // Insert the TLB entry.
668 // The entry specifying whether the address is "real" is set to
669 // false for syscall emulation mode regardless of whether the
670 // address is real in preceding code. Not sure sure that this is
671 // correct, but also not sure if it matters at all.
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 655 unchanged lines hidden (view full) ---

664 // the logic works out to the following for the context.
665 int context_id = (is_real_address || trapped) ? 0 : primary_context;
666
667 // Insert the TLB entry.
668 // The entry specifying whether the address is "real" is set to
669 // false for syscall emulation mode regardless of whether the
670 // address is real in preceding code. Not sure sure that this is
671 // correct, but also not sure if it matters at all.
672 tc->getITBPtr()->insert(alignedvaddr, partition_id, context_id,
673 false, entry.pte);
672 dynamic_cast<TLB *>(tc->getITBPtr())->
673 insert(alignedvaddr, partition_id, context_id, false, entry.pte);
674 }
675}
676
677void
678FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
679{
680 if (FullSystem) {
681 SparcFaultBase::invoke(tc, inst);

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752 // The partition id distinguishes between virtualized environments.
753 int const partition_id = 0;
754
755 // Insert the TLB entry.
756 // The entry specifying whether the address is "real" is set to
757 // false for syscall emulation mode regardless of whether the
758 // address is real in preceding code. Not sure sure that this is
759 // correct, but also not sure if it matters at all.
674 }
675}
676
677void
678FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
679{
680 if (FullSystem) {
681 SparcFaultBase::invoke(tc, inst);

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752 // The partition id distinguishes between virtualized environments.
753 int const partition_id = 0;
754
755 // Insert the TLB entry.
756 // The entry specifying whether the address is "real" is set to
757 // false for syscall emulation mode regardless of whether the
758 // address is real in preceding code. Not sure sure that this is
759 // correct, but also not sure if it matters at all.
760 tc->getDTBPtr()->insert(alignedvaddr, partition_id, context_id,
761 false, entry.pte);
760 dynamic_cast<TLB *>(tc->getDTBPtr())->
761 insert(alignedvaddr, partition_id, context_id, false, entry.pte);
762 }
763}
764
765void
766SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
767{
768 if (FullSystem) {
769 SparcFaultBase::invoke(tc, inst);

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763}
764
765void
766SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
767{
768 if (FullSystem) {
769 SparcFaultBase::invoke(tc, inst);

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