faults.cc (11801:cd7f3a1dbf55) faults.cc (11850:36119fa7874d)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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623 }
624
625 Process *p = tc->getProcessPtr();
626 TlbEntry entry;
627 bool success = p->pTable->lookup(vaddr, entry);
628 if (!success) {
629 panic("Tried to execute unmapped address %#x.\n", vaddr);
630 } else {
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 614 unchanged lines hidden (view full) ---

623 }
624
625 Process *p = tc->getProcessPtr();
626 TlbEntry entry;
627 bool success = p->pTable->lookup(vaddr, entry);
628 if (!success) {
629 panic("Tried to execute unmapped address %#x.\n", vaddr);
630 } else {
631 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
632 tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
633 p->_pid /*context id*/, false, entry.pte);
631 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
632
633 // Grab fields used during instruction translation to figure out
634 // which context to use.
635 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
636
637 // Inside a VM, a real address is the address that guest OS would
638 // interpret to be a physical address. To map to the physical address,
639 // it still needs to undergo a translation. The instruction
640 // translation code in the SPARC ITLB code assumes that the context is
641 // zero (kernel-level) if real addressing is being used.
642 bool is_real_address = !bits(tlbdata, 4);
643
644 // The SPARC ITLB code assumes that traps are executed in context
645 // zero so we carry that assumption through here.
646 bool trapped = bits(tlbdata, 18, 16) > 0;
647
648 // The primary context acts as a PASID. It allows the MMU to
649 // distinguish between virtual addresses that would alias to the
650 // same physical address (if two or more processes shared the same
651 // virtual address mapping).
652 int primary_context = bits(tlbdata, 47, 32);
653
654 // The partition id distinguishes between virtualized environments.
655 int const partition_id = 0;
656
657 // Given the assumptions in the translateInst code in the SPARC ITLB,
658 // the logic works out to the following for the context.
659 int context_id = (is_real_address || trapped) ? 0 : primary_context;
660
661 // Insert the TLB entry.
662 // The entry specifying whether the address is "real" is set to
663 // false for syscall emulation mode regardless of whether the
664 // address is real in preceding code. Not sure sure that this is
665 // correct, but also not sure if it matters at all.
666 tc->getITBPtr()->insert(alignedvaddr, partition_id, context_id,
667 false, entry.pte);
634 }
635}
636
637void
638FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
639{
640 if (FullSystem) {
641 SparcFaultBase::invoke(tc, inst);

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647 bool success = p->pTable->lookup(vaddr, entry);
648 if (!success) {
649 if (p->fixupStackFault(vaddr))
650 success = p->pTable->lookup(vaddr, entry);
651 }
652 if (!success) {
653 panic("Tried to access unmapped address %#x.\n", vaddr);
654 } else {
668 }
669}
670
671void
672FastDataAccessMMUMiss::invoke(ThreadContext *tc, const StaticInstPtr &inst)
673{
674 if (FullSystem) {
675 SparcFaultBase::invoke(tc, inst);

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681 bool success = p->pTable->lookup(vaddr, entry);
682 if (!success) {
683 if (p->fixupStackFault(vaddr))
684 success = p->pTable->lookup(vaddr, entry);
685 }
686 if (!success) {
687 panic("Tried to access unmapped address %#x.\n", vaddr);
688 } else {
655 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
656 tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
657 p->_pid /*context id*/, false, entry.pte);
689 Addr alignedvaddr = p->pTable->pageAlign(vaddr);
690
691 // Grab fields used during data translation to figure out
692 // which context to use.
693 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
694
695 // The primary context acts as a PASID. It allows the MMU to
696 // distinguish between virtual addresses that would alias to the
697 // same physical address (if two or more processes shared the same
698 // virtual address mapping). There's a secondary context used in the
699 // DTLB translation code, but it should __probably__ be zero for
700 // syscall emulation code. (The secondary context is used by Solaris
701 // to allow kernel privilege code to access user space code:
702 // [ISBN 0-13-022496-0]:PG199.)
703 int primary_context = bits(tlbdata, 47, 32);
704
705 // "Hyper-Privileged Mode" is in use. There are three main modes of
706 // operation for Sparc: Hyper-Privileged Mode, Privileged Mode, and
707 // User Mode.
708 int hpriv = bits(tlbdata, 0);
709
710 // Reset, Error and Debug state is in use. Something horrible has
711 // happened or the system is operating in Reset Mode.
712 int red = bits(tlbdata, 1);
713
714 // Inside a VM, a real address is the address that guest OS would
715 // interpret to be a physical address. To map to the physical address,
716 // it still needs to undergo a translation. The instruction
717 // translation code in the SPARC ITLB code assumes that the context is
718 // zero (kernel-level) if real addressing is being used.
719 int is_real_address = !bits(tlbdata, 5);
720
721 // Grab the address space identifier register from the thread context.
722 // XXX: Inspecting how setMiscReg and setMiscRegNoEffect behave for
723 // MISCREG_ASI causes me to think that the ASI register implementation
724 // might be bugged. The NoEffect variant changes the ASI register
725 // value in the architectural state while the normal variant changes
726 // the context field in the thread context's currently decoded request
727 // but does not directly affect the ASI register value in the
728 // architectural state. The ASI values and the context field in the
729 // request packet seem to have completely different uses.
730 MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
731 ASI asi = static_cast<ASI>(reg_asi);
732
733 // The SPARC DTLB code assumes that traps are executed in context
734 // zero if the asi value is ASI_IMPLICIT (which is 0x0). There's also
735 // an assumption that the nucleus address space is being used, but
736 // the context is the relevant issue since we need to pass it to TLB.
737 bool trapped = bits(tlbdata, 18, 16) > 0;
738
739 // Given the assumptions in the translateData code in the SPARC DTLB,
740 // the logic works out to the following for the context.
741 int context_id = ((!hpriv && !red && is_real_address) ||
742 asiIsReal(asi) ||
743 (trapped && asi == ASI_IMPLICIT))
744 ? 0 : primary_context;
745
746 // The partition id distinguishes between virtualized environments.
747 int const partition_id = 0;
748
749 // Insert the TLB entry.
750 // The entry specifying whether the address is "real" is set to
751 // false for syscall emulation mode regardless of whether the
752 // address is real in preceding code. Not sure sure that this is
753 // correct, but also not sure if it matters at all.
754 tc->getDTBPtr()->insert(alignedvaddr, partition_id, context_id,
755 false, entry.pte);
658 }
659}
660
661void
662SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
663{
664 if (FullSystem) {
665 SparcFaultBase::invoke(tc, inst);

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757}
758
759void
760SpillNNormal::invoke(ThreadContext *tc, const StaticInstPtr &inst)
761{
762 if (FullSystem) {
763 SparcFaultBase::invoke(tc, inst);

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