275c275,276
< void enterREDState(ThreadContext *tc)
---
> void
> enterREDState(ThreadContext *tc)
280c281
< //HPSTATE.red = 1
---
> // HPSTATE.red = 1
282c283
< //HPSTATE.hpriv = 1
---
> // HPSTATE.hpriv = 1
285,286c286,287
< //PSTATE.priv is set to 1 here. The manual says it should be 0, but
< //Legion sets it to 1.
---
> // PSTATE.priv is set to 1 here. The manual says it should be 0, but
> // Legion sets it to 1.
297c298,299
< void doREDFault(ThreadContext *tc, TrapType tt)
---
> void
> doREDFault(ThreadContext *tc, TrapType tt)
303d304
< //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
307d307
< //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
316c316
< //set TSTATE.gl to gl
---
> // set TSTATE.gl to gl
318c318
< //set TSTATE.ccr to ccr
---
> // set TSTATE.ccr to ccr
320c320
< //set TSTATE.asi to asi
---
> // set TSTATE.asi to asi
322c322
< //set TSTATE.pstate to pstate
---
> // set TSTATE.pstate to pstate
324c324
< //set TSTATE.cwp to cwp
---
> // set TSTATE.cwp to cwp
327c327
< //Write back TSTATE
---
> // Write back TSTATE
330c330
< //set TPC to PC
---
> // set TPC to PC
332c332
< //set TNPC to NPC
---
> // set TNPC to NPC
335c335
< //set HTSTATE.hpstate to hpstate
---
> // set HTSTATE.hpstate to hpstate
338c338
< //TT = trap type;
---
> // TT = trap type;
341c341
< //Update GL
---
> // Update GL
345c345
< PSTATE |= (1 << 4); //set PSTATE.pef to 1
---
> PSTATE |= (1 << 4); // set PSTATE.pef to 1
348c348
< //set HPSTATE.red to 1
---
> // set HPSTATE.red to 1
350c350
< //set HPSTATE.hpriv to 1
---
> // set HPSTATE.hpriv to 1
352c352
< //set HPSTATE.ibe to 0
---
> // set HPSTATE.ibe to 0
354c354
< //set HPSTATE.tlz to 0
---
> // set HPSTATE.tlz to 0
359c359
< if(tt == 0x24)
---
> if (tt == 0x24)
361c361
< else if(0x80 <= tt && tt <= 0xbf)
---
> else if (0x80 <= tt && tt <= 0xbf)
363c363
< else if(0xc0 <= tt && tt <= 0xff)
---
> else if (0xc0 <= tt && tt <= 0xff)
368,369c368
< if(changedCWP)
< {
---
> if (changedCWP) {
380c379,380
< void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
---
> void
> doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
386d385
< //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
390d388
< //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
395c393
< //Increment the trap level
---
> // Increment the trap level
401c399
< //Save off state
---
> // Save off state
403c401
< //set TSTATE.gl to gl
---
> // set TSTATE.gl to gl
405c403
< //set TSTATE.ccr to ccr
---
> // set TSTATE.ccr to ccr
407c405
< //set TSTATE.asi to asi
---
> // set TSTATE.asi to asi
409c407
< //set TSTATE.pstate to pstate
---
> // set TSTATE.pstate to pstate
411c409
< //set TSTATE.cwp to cwp
---
> // set TSTATE.cwp to cwp
414c412
< //Write back TSTATE
---
> // Write back TSTATE
417c415
< //set TPC to PC
---
> // set TPC to PC
419c417
< //set TNPC to NPC
---
> // set TNPC to NPC
422c420
< //set HTSTATE.hpstate to hpstate
---
> // set HTSTATE.hpstate to hpstate
425c423
< //TT = trap type;
---
> // TT = trap type;
428c426
< //Update the global register level
---
> // Update the global register level
430c428
< tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
---
> tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
432c430
< tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
---
> tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
434,439c432,437
< //PSTATE.mm is unchanged
< PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
< PSTATE &= ~(1 << 3); //PSTATE.am = 0
< PSTATE &= ~(1 << 1); //PSTATE.ie = 0
< //PSTATE.tle is unchanged
< //PSTATE.tct = 0
---
> // PSTATE.mm is unchanged
> PSTATE |= (1 << 4); // PSTATE.pef = whether or not an fpu is present
> PSTATE &= ~(1 << 3); // PSTATE.am = 0
> PSTATE &= ~(1 << 1); // PSTATE.ie = 0
> // PSTATE.tle is unchanged
> // PSTATE.tct = 0
441,442c439
< if (gotoHpriv)
< {
---
> if (gotoHpriv) {
444,448c441,445
< //The manual says PSTATE.priv should be 0, but Legion leaves it alone
< HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
< HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
< HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
< //HPSTATE.tlz is unchanged
---
> // The manual says PSTATE.priv should be 0, but Legion leaves it alone
> HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
> HPSTATE |= (1 << 2); // HPSTATE.hpriv = 1
> HPSTATE &= ~(1 << 10); // HPSTATE.ibe = 0
> // HPSTATE.tlz is unchanged
451,452c448,449
< PSTATE |= (1 << 2); //PSTATE.priv = 1
< replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
---
> PSTATE |= (1 << 2); // PSTATE.priv = 1
> replaceBits(PSTATE, 9, 9, PSTATE >> 8); // PSTATE.cle = PSTATE.tle
467,468c464
< if (changedCWP)
< {
---
> if (changedCWP) {
474c470,471
< void getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
---
> void
> getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
482c479,480
< void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
---
> void
> getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
489c487,488
< void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
---
> void
> getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
500c499,500
< void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
---
> void
> SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
502d501
< //panic("Invoking a second fault!\n");
506,507c505,506
< //We can refer to this to see what the trap level -was-, but something
< //in the middle could change it in the regfile out from under us.
---
> // We can refer to this to see what the trap level -was-, but something
> // in the middle could change it in the regfile out from under us.
528,529c527,528
< //This changes the hpstate and pstate, so we need to make sure we
< //save the old version on the trap stack in doREDFault.
---
> // This changes the hpstate and pstate, so we need to make sure we
> // save the old version on the trap stack in doREDFault.
533,535c532,534
< //Do error_state somehow?
< //Probably inject a WDR fault using the interrupt mechanism.
< //What should the PC and NPC be set to?
---
> // Do error_state somehow?
> // Probably inject a WDR fault using the interrupt mechanism.
> // What should the PC and NPC be set to?
537c536
< //guest_watchdog fault
---
> // guest_watchdog fault
546c545
< getPrivVector(tc, PC, NPC, trapType(), tl+1);
---
> getPrivVector(tc, PC, NPC, trapType(), tl + 1);
558c557,558
< void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
---
> void
> PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
560,562c560,562
< //For SPARC, when a system is first started, there is a power
< //on reset Trap which sets the processor into the following state.
< //Bits that aren't set aren't defined on startup.
---
> // For SPARC, when a system is first started, there is a power
> // on reset Trap which sets the processor into the following state.
> // Bits that aren't set aren't defined on startup.
568c568
< //Turn on pef and priv, set everything else to 0
---
> // Turn on pef and priv, set everything else to 0
571c571
< //Turn on red and hpriv, set everything else to 0
---
> // Turn on red and hpriv, set everything else to 0
573c573
< //HPSTATE.red = 1
---
> // HPSTATE.red = 1
575c575
< //HPSTATE.hpriv = 1
---
> // HPSTATE.hpriv = 1
577c577
< //HPSTATE.ibe = 0
---
> // HPSTATE.ibe = 0
579c579
< //HPSTATE.tlz = 0
---
> // HPSTATE.tlz = 0
583c583
< //The tick register is unreadable by nonprivileged software
---
> // The tick register is unreadable by nonprivileged software
586,587c586,587
< //Enter RED state. We do this last so that the actual state preserved in
< //the trap stack is the state from before this fault.
---
> // Enter RED state. We do this last so that the actual state preserved in
> // the trap stack is the state from before this fault.
601,602c601,602
< //These registers are specified as "undefined" after a POR, and they
< //should have reasonable values after the miscregfile is reset
---
> // These registers are specified as "undefined" after a POR, and they
> // should have reasonable values after the miscregfile is reset
610c610
< stickFields.npt = 1; //The TICK register is unreadable by by !priv
---
> stickFields.npt = 1; // The TICK register is unreadable by by !priv
624,625c624,625
< void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
< StaticInstPtr inst)
---
> void
> FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
630c630
< if(!success) {
---
> if (!success) {
639c639,640
< void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
644c645
< if(!success) {
---
> if (!success) {
648c649
< if(!success) {
---
> if (!success) {
657c658,659
< void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
667c669
< //Then adjust the PC and NPC
---
> // Then adjust the PC and NPC
671c673,674
< void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
675c678
< Process * p = tc->getProcessPtr();
---
> Process *p = tc->getProcessPtr();
681c684
< //Then adjust the PC and NPC
---
> // Then adjust the PC and NPC
685c688,689
< void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
687,689c691,693
< //In SE, this mechanism is how the process requests a service from the
< //operating system. We'll get the process object from the thread context
< //and let it service the request.
---
> // In SE, this mechanism is how the process requests a service from the
> // operating system. We'll get the process object from the thread context
> // and let it service the request.
698,699c702,703
< //We need to explicitly advance the pc, since that's not done for us
< //on a faulting instruction
---
> // We need to explicitly advance the pc, since that's not done for us
> // on a faulting instruction
< void enterREDState(ThreadContext *tc)
---
> void
> enterREDState(ThreadContext *tc)
280c281
< //HPSTATE.red = 1
---
> // HPSTATE.red = 1
282c283
< //HPSTATE.hpriv = 1
---
> // HPSTATE.hpriv = 1
285,286c286,287
< //PSTATE.priv is set to 1 here. The manual says it should be 0, but
< //Legion sets it to 1.
---
> // PSTATE.priv is set to 1 here. The manual says it should be 0, but
> // Legion sets it to 1.
297c298,299
< void doREDFault(ThreadContext *tc, TrapType tt)
---
> void
> doREDFault(ThreadContext *tc, TrapType tt)
303d304
< //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
307d307
< //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
316c316
< //set TSTATE.gl to gl
---
> // set TSTATE.gl to gl
318c318
< //set TSTATE.ccr to ccr
---
> // set TSTATE.ccr to ccr
320c320
< //set TSTATE.asi to asi
---
> // set TSTATE.asi to asi
322c322
< //set TSTATE.pstate to pstate
---
> // set TSTATE.pstate to pstate
324c324
< //set TSTATE.cwp to cwp
---
> // set TSTATE.cwp to cwp
327c327
< //Write back TSTATE
---
> // Write back TSTATE
330c330
< //set TPC to PC
---
> // set TPC to PC
332c332
< //set TNPC to NPC
---
> // set TNPC to NPC
335c335
< //set HTSTATE.hpstate to hpstate
---
> // set HTSTATE.hpstate to hpstate
338c338
< //TT = trap type;
---
> // TT = trap type;
341c341
< //Update GL
---
> // Update GL
345c345
< PSTATE |= (1 << 4); //set PSTATE.pef to 1
---
> PSTATE |= (1 << 4); // set PSTATE.pef to 1
348c348
< //set HPSTATE.red to 1
---
> // set HPSTATE.red to 1
350c350
< //set HPSTATE.hpriv to 1
---
> // set HPSTATE.hpriv to 1
352c352
< //set HPSTATE.ibe to 0
---
> // set HPSTATE.ibe to 0
354c354
< //set HPSTATE.tlz to 0
---
> // set HPSTATE.tlz to 0
359c359
< if(tt == 0x24)
---
> if (tt == 0x24)
361c361
< else if(0x80 <= tt && tt <= 0xbf)
---
> else if (0x80 <= tt && tt <= 0xbf)
363c363
< else if(0xc0 <= tt && tt <= 0xff)
---
> else if (0xc0 <= tt && tt <= 0xff)
368,369c368
< if(changedCWP)
< {
---
> if (changedCWP) {
380c379,380
< void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
---
> void
> doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
386d385
< //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
390d388
< //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
395c393
< //Increment the trap level
---
> // Increment the trap level
401c399
< //Save off state
---
> // Save off state
403c401
< //set TSTATE.gl to gl
---
> // set TSTATE.gl to gl
405c403
< //set TSTATE.ccr to ccr
---
> // set TSTATE.ccr to ccr
407c405
< //set TSTATE.asi to asi
---
> // set TSTATE.asi to asi
409c407
< //set TSTATE.pstate to pstate
---
> // set TSTATE.pstate to pstate
411c409
< //set TSTATE.cwp to cwp
---
> // set TSTATE.cwp to cwp
414c412
< //Write back TSTATE
---
> // Write back TSTATE
417c415
< //set TPC to PC
---
> // set TPC to PC
419c417
< //set TNPC to NPC
---
> // set TNPC to NPC
422c420
< //set HTSTATE.hpstate to hpstate
---
> // set HTSTATE.hpstate to hpstate
425c423
< //TT = trap type;
---
> // TT = trap type;
428c426
< //Update the global register level
---
> // Update the global register level
430c428
< tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
---
> tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxPGL));
432c430
< tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
---
> tc->setMiscReg(MISCREG_GL, min<int>(GL + 1, MaxGL));
434,439c432,437
< //PSTATE.mm is unchanged
< PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
< PSTATE &= ~(1 << 3); //PSTATE.am = 0
< PSTATE &= ~(1 << 1); //PSTATE.ie = 0
< //PSTATE.tle is unchanged
< //PSTATE.tct = 0
---
> // PSTATE.mm is unchanged
> PSTATE |= (1 << 4); // PSTATE.pef = whether or not an fpu is present
> PSTATE &= ~(1 << 3); // PSTATE.am = 0
> PSTATE &= ~(1 << 1); // PSTATE.ie = 0
> // PSTATE.tle is unchanged
> // PSTATE.tct = 0
441,442c439
< if (gotoHpriv)
< {
---
> if (gotoHpriv) {
444,448c441,445
< //The manual says PSTATE.priv should be 0, but Legion leaves it alone
< HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
< HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
< HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
< //HPSTATE.tlz is unchanged
---
> // The manual says PSTATE.priv should be 0, but Legion leaves it alone
> HPSTATE &= ~(1 << 5); // HPSTATE.red = 0
> HPSTATE |= (1 << 2); // HPSTATE.hpriv = 1
> HPSTATE &= ~(1 << 10); // HPSTATE.ibe = 0
> // HPSTATE.tlz is unchanged
451,452c448,449
< PSTATE |= (1 << 2); //PSTATE.priv = 1
< replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
---
> PSTATE |= (1 << 2); // PSTATE.priv = 1
> replaceBits(PSTATE, 9, 9, PSTATE >> 8); // PSTATE.cle = PSTATE.tle
467,468c464
< if (changedCWP)
< {
---
> if (changedCWP) {
474c470,471
< void getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
---
> void
> getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
482c479,480
< void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
---
> void
> getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
489c487,488
< void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
---
> void
> getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
500c499,500
< void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
---
> void
> SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
502d501
< //panic("Invoking a second fault!\n");
506,507c505,506
< //We can refer to this to see what the trap level -was-, but something
< //in the middle could change it in the regfile out from under us.
---
> // We can refer to this to see what the trap level -was-, but something
> // in the middle could change it in the regfile out from under us.
528,529c527,528
< //This changes the hpstate and pstate, so we need to make sure we
< //save the old version on the trap stack in doREDFault.
---
> // This changes the hpstate and pstate, so we need to make sure we
> // save the old version on the trap stack in doREDFault.
533,535c532,534
< //Do error_state somehow?
< //Probably inject a WDR fault using the interrupt mechanism.
< //What should the PC and NPC be set to?
---
> // Do error_state somehow?
> // Probably inject a WDR fault using the interrupt mechanism.
> // What should the PC and NPC be set to?
537c536
< //guest_watchdog fault
---
> // guest_watchdog fault
546c545
< getPrivVector(tc, PC, NPC, trapType(), tl+1);
---
> getPrivVector(tc, PC, NPC, trapType(), tl + 1);
558c557,558
< void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
---
> void
> PowerOnReset::invoke(ThreadContext *tc, StaticInstPtr inst)
560,562c560,562
< //For SPARC, when a system is first started, there is a power
< //on reset Trap which sets the processor into the following state.
< //Bits that aren't set aren't defined on startup.
---
> // For SPARC, when a system is first started, there is a power
> // on reset Trap which sets the processor into the following state.
> // Bits that aren't set aren't defined on startup.
568c568
< //Turn on pef and priv, set everything else to 0
---
> // Turn on pef and priv, set everything else to 0
571c571
< //Turn on red and hpriv, set everything else to 0
---
> // Turn on red and hpriv, set everything else to 0
573c573
< //HPSTATE.red = 1
---
> // HPSTATE.red = 1
575c575
< //HPSTATE.hpriv = 1
---
> // HPSTATE.hpriv = 1
577c577
< //HPSTATE.ibe = 0
---
> // HPSTATE.ibe = 0
579c579
< //HPSTATE.tlz = 0
---
> // HPSTATE.tlz = 0
583c583
< //The tick register is unreadable by nonprivileged software
---
> // The tick register is unreadable by nonprivileged software
586,587c586,587
< //Enter RED state. We do this last so that the actual state preserved in
< //the trap stack is the state from before this fault.
---
> // Enter RED state. We do this last so that the actual state preserved in
> // the trap stack is the state from before this fault.
601,602c601,602
< //These registers are specified as "undefined" after a POR, and they
< //should have reasonable values after the miscregfile is reset
---
> // These registers are specified as "undefined" after a POR, and they
> // should have reasonable values after the miscregfile is reset
610c610
< stickFields.npt = 1; //The TICK register is unreadable by by !priv
---
> stickFields.npt = 1; // The TICK register is unreadable by by !priv
624,625c624,625
< void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
< StaticInstPtr inst)
---
> void
> FastInstructionAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
630c630
< if(!success) {
---
> if (!success) {
639c639,640
< void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
644c645
< if(!success) {
---
> if (!success) {
648c649
< if(!success) {
---
> if (!success) {
657c658,659
< void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
667c669
< //Then adjust the PC and NPC
---
> // Then adjust the PC and NPC
671c673,674
< void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
675c678
< Process * p = tc->getProcessPtr();
---
> Process *p = tc->getProcessPtr();
681c684
< //Then adjust the PC and NPC
---
> // Then adjust the PC and NPC
685c688,689
< void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
---
> void
> TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
687,689c691,693
< //In SE, this mechanism is how the process requests a service from the
< //operating system. We'll get the process object from the thread context
< //and let it service the request.
---
> // In SE, this mechanism is how the process requests a service from the
> // operating system. We'll get the process object from the thread context
> // and let it service the request.
698,699c702,703
< //We need to explicitly advance the pc, since that's not done for us
< //on a faulting instruction
---
> // We need to explicitly advance the pc, since that's not done for us
> // on a faulting instruction