1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals =
55 {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals =
59 {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals =
63 {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals =
67 {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals =
71 {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals =
75 {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals =
79 {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals =
88 {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals =
92 {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals =
96 {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals =
110 {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113 SparcFault<FpExceptionIEEE754>::vals =
114 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117 SparcFault<FpExceptionOther>::vals =
118 {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121 SparcFault<TagOverflow>::vals =
122 {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125 SparcFault<CleanWindow>::vals =
126 {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129 SparcFault<DivisionByZero>::vals =
130 {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133 SparcFault<InternalProcessorError>::vals =
134 {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137 SparcFault<InstructionInvalidTSBEntry>::vals =
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141 SparcFault<DataInvalidTSBEntry>::vals =
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145 SparcFault<DataAccessException>::vals =
146 {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154 SparcFault<DataAccessError>::vals =
155 {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158 SparcFault<DataAccessProtection>::vals =
159 {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162 SparcFault<MemAddressNotAligned>::vals =
163 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166 SparcFault<LDDFMemAddressNotAligned>::vals =
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170 SparcFault<STDFMemAddressNotAligned>::vals =
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174 SparcFault<PrivilegedAction>::vals =
175 {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178 SparcFault<LDQFMemAddressNotAligned>::vals =
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182 SparcFault<STQFMemAddressNotAligned>::vals =
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186 SparcFault<InstructionRealTranslationMiss>::vals =
187 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190 SparcFault<DataRealTranslationMiss>::vals =
191 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199 SparcFault<InterruptLevelN>::vals =
200 {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203 SparcFault<HstickMatch>::vals =
204 {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207 SparcFault<TrapLevelZero>::vals =
208 {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211 SparcFault<InterruptVector>::vals =
212 {"interrupt_vector", 0x060, 2630, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215 SparcFault<PAWatchpoint>::vals =
216 {"PA_watchpoint", 0x061, 1209, {H, H, H}};
217
218template<> SparcFaultBase::FaultVals
219 SparcFault<VAWatchpoint>::vals =
220 {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
221
222template<> SparcFaultBase::FaultVals
223 SparcFault<FastInstructionAccessMMUMiss>::vals =
224 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
225
226template<> SparcFaultBase::FaultVals
227 SparcFault<FastDataAccessMMUMiss>::vals =
228 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231 SparcFault<FastDataAccessProtection>::vals =
232 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235 SparcFault<InstructionBreakpoint>::vals =
236 {"instruction_break", 0x076, 610, {H, H, H}};
237
238template<> SparcFaultBase::FaultVals
239 SparcFault<CpuMondo>::vals =
240 {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243 SparcFault<DevMondo>::vals =
244 {"dev_mondo", 0x07D, 1611, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247 SparcFault<ResumableError>::vals =
248 {"resume_error", 0x07E, 3330, {P, P, SH}};
249
250template<> SparcFaultBase::FaultVals
251 SparcFault<SpillNNormal>::vals =
252 {"spill_n_normal", 0x080, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255 SparcFault<SpillNOther>::vals =
256 {"spill_n_other", 0x0A0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259 SparcFault<FillNNormal>::vals =
260 {"fill_n_normal", 0x0C0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263 SparcFault<FillNOther>::vals =
264 {"fill_n_other", 0x0E0, 900, {P, P, H}};
265
266template<> SparcFaultBase::FaultVals
267 SparcFault<TrapInstruction>::vals =
268 {"trap_instruction", 0x100, 1602, {P, P, H}};
269
270#if !FULL_SYSTEM
271template<> SparcFaultBase::FaultVals
272 SparcFault<PageTableFault>::vals =
273 {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
274#endif
275
276/**
277 * This causes the thread context to enter RED state. This causes the side
278 * effects which go with entering RED state because of a trap.
279 */
280
281void enterREDState(ThreadContext *tc)
282{
283 //@todo Disable the mmu?
284 //@todo Disable watchpoints?
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals =
55 {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals =
59 {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals =
63 {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals =
67 {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals =
71 {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals =
75 {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals =
79 {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals =
88 {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals =
92 {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals =
96 {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals =
110 {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113 SparcFault<FpExceptionIEEE754>::vals =
114 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117 SparcFault<FpExceptionOther>::vals =
118 {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121 SparcFault<TagOverflow>::vals =
122 {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125 SparcFault<CleanWindow>::vals =
126 {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129 SparcFault<DivisionByZero>::vals =
130 {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133 SparcFault<InternalProcessorError>::vals =
134 {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137 SparcFault<InstructionInvalidTSBEntry>::vals =
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141 SparcFault<DataInvalidTSBEntry>::vals =
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145 SparcFault<DataAccessException>::vals =
146 {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154 SparcFault<DataAccessError>::vals =
155 {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158 SparcFault<DataAccessProtection>::vals =
159 {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162 SparcFault<MemAddressNotAligned>::vals =
163 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166 SparcFault<LDDFMemAddressNotAligned>::vals =
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170 SparcFault<STDFMemAddressNotAligned>::vals =
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174 SparcFault<PrivilegedAction>::vals =
175 {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178 SparcFault<LDQFMemAddressNotAligned>::vals =
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182 SparcFault<STQFMemAddressNotAligned>::vals =
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186 SparcFault<InstructionRealTranslationMiss>::vals =
187 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190 SparcFault<DataRealTranslationMiss>::vals =
191 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199 SparcFault<InterruptLevelN>::vals =
200 {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203 SparcFault<HstickMatch>::vals =
204 {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207 SparcFault<TrapLevelZero>::vals =
208 {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211 SparcFault<InterruptVector>::vals =
212 {"interrupt_vector", 0x060, 2630, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215 SparcFault<PAWatchpoint>::vals =
216 {"PA_watchpoint", 0x061, 1209, {H, H, H}};
217
218template<> SparcFaultBase::FaultVals
219 SparcFault<VAWatchpoint>::vals =
220 {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
221
222template<> SparcFaultBase::FaultVals
223 SparcFault<FastInstructionAccessMMUMiss>::vals =
224 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
225
226template<> SparcFaultBase::FaultVals
227 SparcFault<FastDataAccessMMUMiss>::vals =
228 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231 SparcFault<FastDataAccessProtection>::vals =
232 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235 SparcFault<InstructionBreakpoint>::vals =
236 {"instruction_break", 0x076, 610, {H, H, H}};
237
238template<> SparcFaultBase::FaultVals
239 SparcFault<CpuMondo>::vals =
240 {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243 SparcFault<DevMondo>::vals =
244 {"dev_mondo", 0x07D, 1611, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247 SparcFault<ResumableError>::vals =
248 {"resume_error", 0x07E, 3330, {P, P, SH}};
249
250template<> SparcFaultBase::FaultVals
251 SparcFault<SpillNNormal>::vals =
252 {"spill_n_normal", 0x080, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255 SparcFault<SpillNOther>::vals =
256 {"spill_n_other", 0x0A0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259 SparcFault<FillNNormal>::vals =
260 {"fill_n_normal", 0x0C0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263 SparcFault<FillNOther>::vals =
264 {"fill_n_other", 0x0E0, 900, {P, P, H}};
265
266template<> SparcFaultBase::FaultVals
267 SparcFault<TrapInstruction>::vals =
268 {"trap_instruction", 0x100, 1602, {P, P, H}};
269
270#if !FULL_SYSTEM
271template<> SparcFaultBase::FaultVals
272 SparcFault<PageTableFault>::vals =
273 {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
274#endif
275
276/**
277 * This causes the thread context to enter RED state. This causes the side
278 * effects which go with entering RED state because of a trap.
279 */
280
281void enterREDState(ThreadContext *tc)
282{
283 //@todo Disable the mmu?
284 //@todo Disable watchpoints?
|
285 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
| 285 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
286 //HPSTATE.red = 1
287 HPSTATE |= (1 << 5);
288 //HPSTATE.hpriv = 1
289 HPSTATE |= (1 << 2);
| 286 //HPSTATE.red = 1
287 HPSTATE |= (1 << 5);
288 //HPSTATE.hpriv = 1
289 HPSTATE |= (1 << 2);
|
290 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
| 290 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
|
291 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
292 //Legion sets it to 1.
| 291 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
292 //Legion sets it to 1.
|
293 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
| 293 MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
|
294 PSTATE |= (1 << 2);
| 294 PSTATE |= (1 << 2);
|
295 tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
| 295 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
|
296}
297
298/**
299 * This sets everything up for a RED state trap except for actually jumping to
300 * the handler.
301 */
302
303void doREDFault(ThreadContext *tc, TrapType tt)
304{
| 296}
297
298/**
299 * This sets everything up for a RED state trap except for actually jumping to
300 * the handler.
301 */
302
303void doREDFault(ThreadContext *tc, TrapType tt)
304{
|
305 MiscReg TL = tc->readMiscReg(MISCREG_TL);
306 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
307 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
308 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
309 //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
| 305 MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
306 MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
307 MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
308 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
309 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
|
310 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
| 310 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
|
311 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
312 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
313 //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
314 MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
315 MiscReg GL = tc->readMiscReg(MISCREG_GL);
| 311 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
312 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
313 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
314 MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
315 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
|
316 MiscReg PC = tc->readPC();
317 MiscReg NPC = tc->readNextPC();
318
319 TL++;
320
321 if (bits(PSTATE, 3,3)) {
322 PC &= mask(32);
323 NPC &= mask(32);
324 }
325
326 //set TSTATE.gl to gl
327 replaceBits(TSTATE, 42, 40, GL);
328 //set TSTATE.ccr to ccr
329 replaceBits(TSTATE, 39, 32, CCR);
330 //set TSTATE.asi to asi
331 replaceBits(TSTATE, 31, 24, ASI);
332 //set TSTATE.pstate to pstate
333 replaceBits(TSTATE, 20, 8, PSTATE);
334 //set TSTATE.cwp to cwp
335 replaceBits(TSTATE, 4, 0, CWP);
336
337 //Write back TSTATE
| 316 MiscReg PC = tc->readPC();
317 MiscReg NPC = tc->readNextPC();
318
319 TL++;
320
321 if (bits(PSTATE, 3,3)) {
322 PC &= mask(32);
323 NPC &= mask(32);
324 }
325
326 //set TSTATE.gl to gl
327 replaceBits(TSTATE, 42, 40, GL);
328 //set TSTATE.ccr to ccr
329 replaceBits(TSTATE, 39, 32, CCR);
330 //set TSTATE.asi to asi
331 replaceBits(TSTATE, 31, 24, ASI);
332 //set TSTATE.pstate to pstate
333 replaceBits(TSTATE, 20, 8, PSTATE);
334 //set TSTATE.cwp to cwp
335 replaceBits(TSTATE, 4, 0, CWP);
336
337 //Write back TSTATE
|
338 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
| 338 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
|
339
340 //set TPC to PC
| 339
340 //set TPC to PC
|
341 tc->setMiscReg(MISCREG_TPC, PC);
| 341 tc->setMiscRegNoEffect(MISCREG_TPC, PC);
|
342 //set TNPC to NPC
| 342 //set TNPC to NPC
|
343 tc->setMiscReg(MISCREG_TNPC, NPC);
| 343 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
|
344
345 //set HTSTATE.hpstate to hpstate
| 344
345 //set HTSTATE.hpstate to hpstate
|
346 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
| 346 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
|
347
348 //TT = trap type;
| 347
348 //TT = trap type;
|
349 tc->setMiscReg(MISCREG_TT, tt);
| 349 tc->setMiscRegNoEffect(MISCREG_TT, tt);
|
350
351 //Update GL
| 350
351 //Update GL
|
352 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
| 352 tc->setMiscReg(MISCREG_GL, min(GL+1, MaxGL));
|
353
354 PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
355 PSTATE |= (1 << 4); //set PSTATE.pef to 1
| 353
354 PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
355 PSTATE |= (1 << 4); //set PSTATE.pef to 1
|
356 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
| 356 tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
|
357
358 //set HPSTATE.red to 1
359 HPSTATE |= (1 << 5);
360 //set HPSTATE.hpriv to 1
361 HPSTATE |= (1 << 2);
362 //set HPSTATE.ibe to 0
363 HPSTATE &= ~(1 << 10);
364 //set HPSTATE.tlz to 0
365 HPSTATE &= ~(1 << 0);
| 357
358 //set HPSTATE.red to 1
359 HPSTATE |= (1 << 5);
360 //set HPSTATE.hpriv to 1
361 HPSTATE |= (1 << 2);
362 //set HPSTATE.ibe to 0
363 HPSTATE &= ~(1 << 10);
364 //set HPSTATE.tlz to 0
365 HPSTATE &= ~(1 << 0);
|
366 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
| 366 tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
|
367
368 bool changedCWP = true;
369 if(tt == 0x24)
370 CWP++;
371 else if(0x80 <= tt && tt <= 0xbf)
372 CWP += (CANSAVE + 2);
373 else if(0xc0 <= tt && tt <= 0xff)
374 CWP--;
375 else
376 changedCWP = false;
377
378 if(changedCWP)
379 {
380 CWP = (CWP + NWindows) % NWindows;
| 367
368 bool changedCWP = true;
369 if(tt == 0x24)
370 CWP++;
371 else if(0x80 <= tt && tt <= 0xbf)
372 CWP += (CANSAVE + 2);
373 else if(0xc0 <= tt && tt <= 0xff)
374 CWP--;
375 else
376 changedCWP = false;
377
378 if(changedCWP)
379 {
380 CWP = (CWP + NWindows) % NWindows;
|
381 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
| 381 tc->setMiscReg(MISCREG_CWP, CWP);
|
382 }
383}
384
385/**
386 * This sets everything up for a normal trap except for actually jumping to
387 * the handler.
388 */
389
390void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
391{
| 382 }
383}
384
385/**
386 * This sets everything up for a normal trap except for actually jumping to
387 * the handler.
388 */
389
390void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
391{
|
392 MiscReg TL = tc->readMiscReg(MISCREG_TL);
393 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
394 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
395 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
396 //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
| 392 MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
393 MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
394 MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
395 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
396 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
|
397 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
| 397 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
|
398 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
399 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
400 //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
| 398 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
399 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
400 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
|
401 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
| 401 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
|
402 MiscReg GL = tc->readMiscReg(MISCREG_GL);
| 402 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
|
403 MiscReg PC = tc->readPC();
404 MiscReg NPC = tc->readNextPC();
405
406 if (bits(PSTATE, 3,3)) {
407 PC &= mask(32);
408 NPC &= mask(32);
409 }
410
411 //Increment the trap level
412 TL++;
| 403 MiscReg PC = tc->readPC();
404 MiscReg NPC = tc->readNextPC();
405
406 if (bits(PSTATE, 3,3)) {
407 PC &= mask(32);
408 NPC &= mask(32);
409 }
410
411 //Increment the trap level
412 TL++;
|
413 tc->setMiscReg(MISCREG_TL, TL);
| 413 tc->setMiscRegNoEffect(MISCREG_TL, TL);
|
414
415 //Save off state
416
417 //set TSTATE.gl to gl
418 replaceBits(TSTATE, 42, 40, GL);
419 //set TSTATE.ccr to ccr
420 replaceBits(TSTATE, 39, 32, CCR);
421 //set TSTATE.asi to asi
422 replaceBits(TSTATE, 31, 24, ASI);
423 //set TSTATE.pstate to pstate
424 replaceBits(TSTATE, 20, 8, PSTATE);
425 //set TSTATE.cwp to cwp
426 replaceBits(TSTATE, 4, 0, CWP);
427
428 //Write back TSTATE
| 414
415 //Save off state
416
417 //set TSTATE.gl to gl
418 replaceBits(TSTATE, 42, 40, GL);
419 //set TSTATE.ccr to ccr
420 replaceBits(TSTATE, 39, 32, CCR);
421 //set TSTATE.asi to asi
422 replaceBits(TSTATE, 31, 24, ASI);
423 //set TSTATE.pstate to pstate
424 replaceBits(TSTATE, 20, 8, PSTATE);
425 //set TSTATE.cwp to cwp
426 replaceBits(TSTATE, 4, 0, CWP);
427
428 //Write back TSTATE
|
429 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
| 429 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
|
430
431 //set TPC to PC
| 430
431 //set TPC to PC
|
432 tc->setMiscReg(MISCREG_TPC, PC);
| 432 tc->setMiscRegNoEffect(MISCREG_TPC, PC);
|
433 //set TNPC to NPC
| 433 //set TNPC to NPC
|
434 tc->setMiscReg(MISCREG_TNPC, NPC);
| 434 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
|
435
436 //set HTSTATE.hpstate to hpstate
| 435
436 //set HTSTATE.hpstate to hpstate
|
437 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
| 437 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
|
438
439 //TT = trap type;
| 438
439 //TT = trap type;
|
440 tc->setMiscReg(MISCREG_TT, tt);
| 440 tc->setMiscRegNoEffect(MISCREG_TT, tt);
|
441
442 //Update the global register level
443 if (!gotoHpriv)
| 441
442 //Update the global register level
443 if (!gotoHpriv)
|
444 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
| 444 tc->setMiscReg(MISCREG_GL, min(GL+1, MaxPGL));
|
445 else
| 445 else
|
446 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
| 446 tc->setMiscReg(MISCREG_GL, min(GL+1, MaxGL));
|
447
448 //PSTATE.mm is unchanged
449 PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
450 PSTATE &= ~(1 << 3); //PSTATE.am = 0
451 PSTATE &= ~(1 << 1); //PSTATE.ie = 0
452 //PSTATE.tle is unchanged
453 //PSTATE.tct = 0
454
455 if (gotoHpriv)
456 {
457 PSTATE &= ~(1 << 9); // PSTATE.cle = 0
458 //The manual says PSTATE.priv should be 0, but Legion leaves it alone
459 HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
460 HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
461 HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
462 //HPSTATE.tlz is unchanged
| 447
448 //PSTATE.mm is unchanged
449 PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
450 PSTATE &= ~(1 << 3); //PSTATE.am = 0
451 PSTATE &= ~(1 << 1); //PSTATE.ie = 0
452 //PSTATE.tle is unchanged
453 //PSTATE.tct = 0
454
455 if (gotoHpriv)
456 {
457 PSTATE &= ~(1 << 9); // PSTATE.cle = 0
458 //The manual says PSTATE.priv should be 0, but Legion leaves it alone
459 HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
460 HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
461 HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
462 //HPSTATE.tlz is unchanged
|
463 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
| 463 tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
|
464 } else { // we are going to priv
465 PSTATE |= (1 << 2); //PSTATE.priv = 1
466 replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
467 }
| 464 } else { // we are going to priv
465 PSTATE |= (1 << 2); //PSTATE.priv = 1
466 replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
467 }
|
468 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
| 468 tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
|
469
470
471 bool changedCWP = true;
472 if (tt == 0x24)
473 CWP++;
474 else if (0x80 <= tt && tt <= 0xbf)
475 CWP += (CANSAVE + 2);
476 else if (0xc0 <= tt && tt <= 0xff)
477 CWP--;
478 else
479 changedCWP = false;
480
481 if (changedCWP)
482 {
483 CWP = (CWP + NWindows) % NWindows;
| 469
470
471 bool changedCWP = true;
472 if (tt == 0x24)
473 CWP++;
474 else if (0x80 <= tt && tt <= 0xbf)
475 CWP += (CANSAVE + 2);
476 else if (0xc0 <= tt && tt <= 0xff)
477 CWP--;
478 else
479 changedCWP = false;
480
481 if (changedCWP)
482 {
483 CWP = (CWP + NWindows) % NWindows;
|
484 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
| 484 tc->setMiscReg(MISCREG_CWP, CWP);
|
485 }
486}
487
488void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
489{
490 //XXX The following constant might belong in a header file.
491 const Addr RSTVAddr = 0xFFF0000000ULL;
492 PC = RSTVAddr | ((TT << 5) & 0xFF);
493 NPC = PC + sizeof(MachInst);
494}
495
496void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
497{
| 485 }
486}
487
488void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
489{
490 //XXX The following constant might belong in a header file.
491 const Addr RSTVAddr = 0xFFF0000000ULL;
492 PC = RSTVAddr | ((TT << 5) & 0xFF);
493 NPC = PC + sizeof(MachInst);
494}
495
496void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
497{
|
498 Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
| 498 Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
|
499 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
500 NPC = PC + sizeof(MachInst);
501}
502
503void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
504{
| 499 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
500 NPC = PC + sizeof(MachInst);
501}
502
503void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
504{
|
505 Addr TBA = tc->readMiscReg(MISCREG_TBA);
| 505 Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
|
506 PC = (TBA & ~mask(15)) |
507 (TL > 1 ? (1 << 14) : 0) |
508 ((TT << 5) & mask(14));
509 NPC = PC + sizeof(MachInst);
510}
511
512#if FULL_SYSTEM
513
514void SparcFaultBase::invoke(ThreadContext * tc)
515{
516 //panic("Invoking a second fault!\n");
517 FaultBase::invoke(tc);
518 countStat()++;
519
520 //We can refer to this to see what the trap level -was-, but something
521 //in the middle could change it in the regfile out from under us.
| 506 PC = (TBA & ~mask(15)) |
507 (TL > 1 ? (1 << 14) : 0) |
508 ((TT << 5) & mask(14));
509 NPC = PC + sizeof(MachInst);
510}
511
512#if FULL_SYSTEM
513
514void SparcFaultBase::invoke(ThreadContext * tc)
515{
516 //panic("Invoking a second fault!\n");
517 FaultBase::invoke(tc);
518 countStat()++;
519
520 //We can refer to this to see what the trap level -was-, but something
521 //in the middle could change it in the regfile out from under us.
|
522 MiscReg tl = tc->readMiscReg(MISCREG_TL);
523 MiscReg tt = tc->readMiscReg(MISCREG_TT);
524 MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
525 MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
| 522 MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
523 MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
524 MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
525 MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
526
527 Addr PC, NPC;
528
529 PrivilegeLevel current;
530 if (hpstate & HPSTATE::hpriv)
531 current = Hyperprivileged;
532 else if (pstate & PSTATE::priv)
533 current = Privileged;
534 else
535 current = User;
536
537 PrivilegeLevel level = getNextLevel(current);
538
539 if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
540 getREDVector(5, PC, NPC);
541 doREDFault(tc, tt);
542 //This changes the hpstate and pstate, so we need to make sure we
543 //save the old version on the trap stack in doREDFault.
544 enterREDState(tc);
545 } else if (tl == MaxTL) {
546 panic("Should go to error state here.. crap\n");
547 //Do error_state somehow?
548 //Probably inject a WDR fault using the interrupt mechanism.
549 //What should the PC and NPC be set to?
550 } else if (tl > MaxPTL && level == Privileged) {
551 //guest_watchdog fault
552 doNormalFault(tc, trapType(), true);
553 getHyperVector(tc, PC, NPC, 2);
554 } else if (level == Hyperprivileged ||
555 level == Privileged && trapType() >= 384) {
556 doNormalFault(tc, trapType(), true);
557 getHyperVector(tc, PC, NPC, trapType());
558 } else {
559 doNormalFault(tc, trapType(), false);
560 getPrivVector(tc, PC, NPC, trapType(), tl+1);
561 }
562
563 tc->setPC(PC);
564 tc->setNextPC(NPC);
565 tc->setNextNPC(NPC + sizeof(MachInst));
566}
567
568void PowerOnReset::invoke(ThreadContext * tc)
569{
570 //For SPARC, when a system is first started, there is a power
571 //on reset Trap which sets the processor into the following state.
572 //Bits that aren't set aren't defined on startup.
573
| 526
527 Addr PC, NPC;
528
529 PrivilegeLevel current;
530 if (hpstate & HPSTATE::hpriv)
531 current = Hyperprivileged;
532 else if (pstate & PSTATE::priv)
533 current = Privileged;
534 else
535 current = User;
536
537 PrivilegeLevel level = getNextLevel(current);
538
539 if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
540 getREDVector(5, PC, NPC);
541 doREDFault(tc, tt);
542 //This changes the hpstate and pstate, so we need to make sure we
543 //save the old version on the trap stack in doREDFault.
544 enterREDState(tc);
545 } else if (tl == MaxTL) {
546 panic("Should go to error state here.. crap\n");
547 //Do error_state somehow?
548 //Probably inject a WDR fault using the interrupt mechanism.
549 //What should the PC and NPC be set to?
550 } else if (tl > MaxPTL && level == Privileged) {
551 //guest_watchdog fault
552 doNormalFault(tc, trapType(), true);
553 getHyperVector(tc, PC, NPC, 2);
554 } else if (level == Hyperprivileged ||
555 level == Privileged && trapType() >= 384) {
556 doNormalFault(tc, trapType(), true);
557 getHyperVector(tc, PC, NPC, trapType());
558 } else {
559 doNormalFault(tc, trapType(), false);
560 getPrivVector(tc, PC, NPC, trapType(), tl+1);
561 }
562
563 tc->setPC(PC);
564 tc->setNextPC(NPC);
565 tc->setNextNPC(NPC + sizeof(MachInst));
566}
567
568void PowerOnReset::invoke(ThreadContext * tc)
569{
570 //For SPARC, when a system is first started, there is a power
571 //on reset Trap which sets the processor into the following state.
572 //Bits that aren't set aren't defined on startup.
573
|
574 tc->setMiscReg(MISCREG_TL, MaxTL);
575 tc->setMiscReg(MISCREG_TT, trapType());
576 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
| 574 tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
575 tc->setMiscRegNoEffect(MISCREG_TT, trapType());
576 tc->setMiscReg(MISCREG_GL, MaxGL);
|
577
578 //Turn on pef and priv, set everything else to 0
| 577
578 //Turn on pef and priv, set everything else to 0
|
579 tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
| 579 tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
|
580
581 //Turn on red and hpriv, set everything else to 0
| 580
581 //Turn on red and hpriv, set everything else to 0
|
582 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
| 582 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
|
583 //HPSTATE.red = 1
584 HPSTATE |= (1 << 5);
585 //HPSTATE.hpriv = 1
586 HPSTATE |= (1 << 2);
587 //HPSTATE.ibe = 0
588 HPSTATE &= ~(1 << 10);
589 //HPSTATE.tlz = 0
590 HPSTATE &= ~(1 << 0);
| 583 //HPSTATE.red = 1
584 HPSTATE |= (1 << 5);
585 //HPSTATE.hpriv = 1
586 HPSTATE |= (1 << 2);
587 //HPSTATE.ibe = 0
588 HPSTATE &= ~(1 << 10);
589 //HPSTATE.tlz = 0
590 HPSTATE &= ~(1 << 0);
|
591 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
| 591 tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
|
592
593 //The tick register is unreadable by nonprivileged software
| 592
593 //The tick register is unreadable by nonprivileged software
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594 tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
| 594 tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
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595
596 //Enter RED state. We do this last so that the actual state preserved in
597 //the trap stack is the state from before this fault.
598 enterREDState(tc);
599
600 Addr PC, NPC;
601 getREDVector(trapType(), PC, NPC);
602 tc->setPC(PC);
603 tc->setNextPC(NPC);
604 tc->setNextNPC(NPC + sizeof(MachInst));
605
606 //These registers are specified as "undefined" after a POR, and they
607 //should have reasonable values after the miscregfile is reset
608 /*
609 // Clear all the soft interrupt bits
610 softint = 0;
611 // disable timer compare interrupts, reset tick_cmpr
| 595
596 //Enter RED state. We do this last so that the actual state preserved in
597 //the trap stack is the state from before this fault.
598 enterREDState(tc);
599
600 Addr PC, NPC;
601 getREDVector(trapType(), PC, NPC);
602 tc->setPC(PC);
603 tc->setNextPC(NPC);
604 tc->setNextNPC(NPC + sizeof(MachInst));
605
606 //These registers are specified as "undefined" after a POR, and they
607 //should have reasonable values after the miscregfile is reset
608 /*
609 // Clear all the soft interrupt bits
610 softint = 0;
611 // disable timer compare interrupts, reset tick_cmpr
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612 tc->setMiscReg(MISCREG_
| 612 tc->setMiscRegNoEffect(MISCREG_
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613 tick_cmprFields.int_dis = 1;
614 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
615 stickFields.npt = 1; //The TICK register is unreadable by by !priv
616 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
617 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
618
619 tt[tl] = _trapType;
620
621 hintp = 0; // no interrupts pending
622 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
623 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
624 */
625}
626
627#else // !FULL_SYSTEM
628
629void SpillNNormal::invoke(ThreadContext *tc)
630{
631 doNormalFault(tc, trapType(), false);
632
633 Process *p = tc->getProcessPtr();
634
635 //XXX This will only work in faults from a SparcLiveProcess
636 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
637 assert(lp);
638
639 //Then adjust the PC and NPC
640 Addr spillStart = lp->readSpillStart();
641 tc->setPC(spillStart);
642 tc->setNextPC(spillStart + sizeof(MachInst));
643 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
644}
645
646void FillNNormal::invoke(ThreadContext *tc)
647{
648 doNormalFault(tc, trapType(), false);
649
650 Process * p = tc->getProcessPtr();
651
652 //XXX This will only work in faults from a SparcLiveProcess
653 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
654 assert(lp);
655
656 //Then adjust the PC and NPC
657 Addr fillStart = lp->readFillStart();
658 tc->setPC(fillStart);
659 tc->setNextPC(fillStart + sizeof(MachInst));
660 tc->setNextNPC(fillStart + 2*sizeof(MachInst));
661}
662
663void TrapInstruction::invoke(ThreadContext *tc)
664{
665 //In SE, this mechanism is how the process requests a service from the
666 //operating system. We'll get the process object from the thread context
667 //and let it service the request.
668
669 Process *p = tc->getProcessPtr();
670
671 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
672 assert(lp);
673
674 lp->handleTrap(_n, tc);
675
676 //We need to explicitly advance the pc, since that's not done for us
677 //on a faulting instruction
678 tc->setPC(tc->readNextPC());
679 tc->setNextPC(tc->readNextNPC());
680 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
681}
682
683void PageTableFault::invoke(ThreadContext *tc)
684{
685 Process *p = tc->getProcessPtr();
686
687 // We've accessed the next page of the stack, so extend the stack
688 // to cover it.
689 if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes)
690 {
691 p->stack_min -= PageBytes;
692 if(p->stack_base - p->stack_min > 8*1024*1024)
693 fatal("Over max stack size for one thread\n");
694 p->pTable->allocate(p->stack_min, PageBytes);
695 warn("Increasing stack size by one page.");
696 }
697 // Otherwise, we have an unexpected page fault. Report that fact,
698 // and what address was accessed to cause the fault.
699 else
700 {
701 panic("Page table fault when accessing virtual address %#x\n", vaddr);
702 }
703}
704
705#endif
706
707} // namespace SparcISA
708
| 613 tick_cmprFields.int_dis = 1;
614 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
615 stickFields.npt = 1; //The TICK register is unreadable by by !priv
616 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
617 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
618
619 tt[tl] = _trapType;
620
621 hintp = 0; // no interrupts pending
622 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
623 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
624 */
625}
626
627#else // !FULL_SYSTEM
628
629void SpillNNormal::invoke(ThreadContext *tc)
630{
631 doNormalFault(tc, trapType(), false);
632
633 Process *p = tc->getProcessPtr();
634
635 //XXX This will only work in faults from a SparcLiveProcess
636 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
637 assert(lp);
638
639 //Then adjust the PC and NPC
640 Addr spillStart = lp->readSpillStart();
641 tc->setPC(spillStart);
642 tc->setNextPC(spillStart + sizeof(MachInst));
643 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
644}
645
646void FillNNormal::invoke(ThreadContext *tc)
647{
648 doNormalFault(tc, trapType(), false);
649
650 Process * p = tc->getProcessPtr();
651
652 //XXX This will only work in faults from a SparcLiveProcess
653 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
654 assert(lp);
655
656 //Then adjust the PC and NPC
657 Addr fillStart = lp->readFillStart();
658 tc->setPC(fillStart);
659 tc->setNextPC(fillStart + sizeof(MachInst));
660 tc->setNextNPC(fillStart + 2*sizeof(MachInst));
661}
662
663void TrapInstruction::invoke(ThreadContext *tc)
664{
665 //In SE, this mechanism is how the process requests a service from the
666 //operating system. We'll get the process object from the thread context
667 //and let it service the request.
668
669 Process *p = tc->getProcessPtr();
670
671 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
672 assert(lp);
673
674 lp->handleTrap(_n, tc);
675
676 //We need to explicitly advance the pc, since that's not done for us
677 //on a faulting instruction
678 tc->setPC(tc->readNextPC());
679 tc->setNextPC(tc->readNextNPC());
680 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
681}
682
683void PageTableFault::invoke(ThreadContext *tc)
684{
685 Process *p = tc->getProcessPtr();
686
687 // We've accessed the next page of the stack, so extend the stack
688 // to cover it.
689 if(vaddr < p->stack_min && vaddr >= p->stack_min - PageBytes)
690 {
691 p->stack_min -= PageBytes;
692 if(p->stack_base - p->stack_min > 8*1024*1024)
693 fatal("Over max stack size for one thread\n");
694 p->pTable->allocate(p->stack_min, PageBytes);
695 warn("Increasing stack size by one page.");
696 }
697 // Otherwise, we have an unexpected page fault. Report that fact,
698 // and what address was accessed to cause the fault.
699 else
700 {
701 panic("Page table fault when accessing virtual address %#x\n", vaddr);
702 }
703}
704
705#endif
706
707} // namespace SparcISA
708
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