faults.cc (3893:e2a358430839) faults.cc (3926:c57925da8d38)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals =
55 {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals =
59 {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals =
63 {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals =
67 {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals =
71 {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals =
75 {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals =
79 {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals =
88 {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals =
92 {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals =
96 {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals =
110 {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113 SparcFault<FpExceptionIEEE754>::vals =
114 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117 SparcFault<FpExceptionOther>::vals =
118 {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121 SparcFault<TagOverflow>::vals =
122 {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125 SparcFault<CleanWindow>::vals =
126 {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129 SparcFault<DivisionByZero>::vals =
130 {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133 SparcFault<InternalProcessorError>::vals =
134 {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137 SparcFault<InstructionInvalidTSBEntry>::vals =
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141 SparcFault<DataInvalidTSBEntry>::vals =
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145 SparcFault<DataAccessException>::vals =
146 {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154 SparcFault<DataAccessError>::vals =
155 {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158 SparcFault<DataAccessProtection>::vals =
159 {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162 SparcFault<MemAddressNotAligned>::vals =
163 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166 SparcFault<LDDFMemAddressNotAligned>::vals =
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170 SparcFault<STDFMemAddressNotAligned>::vals =
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174 SparcFault<PrivilegedAction>::vals =
175 {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178 SparcFault<LDQFMemAddressNotAligned>::vals =
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182 SparcFault<STQFMemAddressNotAligned>::vals =
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186 SparcFault<InstructionRealTranslationMiss>::vals =
187 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190 SparcFault<DataRealTranslationMiss>::vals =
191 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199 SparcFault<InterruptLevelN>::vals =
200 {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203 SparcFault<HstickMatch>::vals =
204 {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207 SparcFault<TrapLevelZero>::vals =
208 {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211 SparcFault<PAWatchpoint>::vals =
212 {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215 SparcFault<VAWatchpoint>::vals =
216 {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219 SparcFault<FastInstructionAccessMMUMiss>::vals =
220 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223 SparcFault<FastDataAccessMMUMiss>::vals =
224 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227 SparcFault<FastDataAccessProtection>::vals =
228 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231 SparcFault<InstructionBreakpoint>::vals =
232 {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235 SparcFault<CpuMondo>::vals =
236 {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239 SparcFault<DevMondo>::vals =
240 {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243 SparcFault<ResumableError>::vals =
244 {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247 SparcFault<SpillNNormal>::vals =
248 {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251 SparcFault<SpillNOther>::vals =
252 {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255 SparcFault<FillNNormal>::vals =
256 {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259 SparcFault<FillNOther>::vals =
260 {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263 SparcFault<TrapInstruction>::vals =
264 {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268 SparcFault<PageTableFault>::vals =
269 {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282 //HPSTATE.red = 1
283 HPSTATE |= (1 << 5);
284 //HPSTATE.hpriv = 1
285 HPSTATE |= (1 << 2);
286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
288 //Legion sets it to 1.
289 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
290 PSTATE |= (1 << 2);
291 tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301 MiscReg TL = tc->readMiscReg(MISCREG_TL);
302 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
307 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
308 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
309 MiscReg GL = tc->readMiscReg(MISCREG_GL);
310 MiscReg PC = tc->readPC();
311 MiscReg NPC = tc->readNextPC();
312
313 TL++;
314
315 //set TSTATE.gl to gl
316 replaceBits(TSTATE, 42, 40, GL);
317 //set TSTATE.ccr to ccr
318 replaceBits(TSTATE, 39, 32, CCR);
319 //set TSTATE.asi to asi
320 replaceBits(TSTATE, 31, 24, ASI);
321 //set TSTATE.pstate to pstate
322 replaceBits(TSTATE, 20, 8, PSTATE);
323 //set TSTATE.cwp to cwp
324 replaceBits(TSTATE, 4, 0, CWP);
325
326 //Write back TSTATE
327 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
328
329 //set TPC to PC
330 tc->setMiscReg(MISCREG_TPC, PC);
331 //set TNPC to NPC
332 tc->setMiscReg(MISCREG_TNPC, NPC);
333
334 //set HTSTATE.hpstate to hpstate
335 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
336
337 //TT = trap type;
338 tc->setMiscReg(MISCREG_TT, tt);
339
340 //Update GL
341 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
342
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Kevin Lim
30 */
31
32#include <algorithm>
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/bitfield.hh"
38#include "base/trace.hh"
39#include "config/full_system.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#if !FULL_SYSTEM
43#include "arch/sparc/process.hh"
44#include "mem/page_table.hh"
45#include "sim/process.hh"
46#endif
47
48using namespace std;
49
50namespace SparcISA
51{
52
53template<> SparcFaultBase::FaultVals
54 SparcFault<PowerOnReset>::vals =
55 {"power_on_reset", 0x001, 0, {H, H, H}};
56
57template<> SparcFaultBase::FaultVals
58 SparcFault<WatchDogReset>::vals =
59 {"watch_dog_reset", 0x002, 120, {H, H, H}};
60
61template<> SparcFaultBase::FaultVals
62 SparcFault<ExternallyInitiatedReset>::vals =
63 {"externally_initiated_reset", 0x003, 110, {H, H, H}};
64
65template<> SparcFaultBase::FaultVals
66 SparcFault<SoftwareInitiatedReset>::vals =
67 {"software_initiated_reset", 0x004, 130, {SH, SH, H}};
68
69template<> SparcFaultBase::FaultVals
70 SparcFault<REDStateException>::vals =
71 {"RED_state_exception", 0x005, 1, {H, H, H}};
72
73template<> SparcFaultBase::FaultVals
74 SparcFault<StoreError>::vals =
75 {"store_error", 0x007, 201, {H, H, H}};
76
77template<> SparcFaultBase::FaultVals
78 SparcFault<InstructionAccessException>::vals =
79 {"instruction_access_exception", 0x008, 300, {H, H, H}};
80
81//XXX This trap is apparently dropped from ua2005
82/*template<> SparcFaultBase::FaultVals
83 SparcFault<InstructionAccessMMUMiss>::vals =
84 {"inst_mmu", 0x009, 2, {H, H, H}};*/
85
86template<> SparcFaultBase::FaultVals
87 SparcFault<InstructionAccessError>::vals =
88 {"instruction_access_error", 0x00A, 400, {H, H, H}};
89
90template<> SparcFaultBase::FaultVals
91 SparcFault<IllegalInstruction>::vals =
92 {"illegal_instruction", 0x010, 620, {H, H, H}};
93
94template<> SparcFaultBase::FaultVals
95 SparcFault<PrivilegedOpcode>::vals =
96 {"privileged_opcode", 0x011, 700, {P, SH, SH}};
97
98//XXX This trap is apparently dropped from ua2005
99/*template<> SparcFaultBase::FaultVals
100 SparcFault<UnimplementedLDD>::vals =
101 {"unimp_ldd", 0x012, 6, {H, H, H}};*/
102
103//XXX This trap is apparently dropped from ua2005
104/*template<> SparcFaultBase::FaultVals
105 SparcFault<UnimplementedSTD>::vals =
106 {"unimp_std", 0x013, 6, {H, H, H}};*/
107
108template<> SparcFaultBase::FaultVals
109 SparcFault<FpDisabled>::vals =
110 {"fp_disabled", 0x020, 800, {P, P, H}};
111
112template<> SparcFaultBase::FaultVals
113 SparcFault<FpExceptionIEEE754>::vals =
114 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}};
115
116template<> SparcFaultBase::FaultVals
117 SparcFault<FpExceptionOther>::vals =
118 {"fp_exception_other", 0x022, 1110, {P, P, H}};
119
120template<> SparcFaultBase::FaultVals
121 SparcFault<TagOverflow>::vals =
122 {"tag_overflow", 0x023, 1400, {P, P, H}};
123
124template<> SparcFaultBase::FaultVals
125 SparcFault<CleanWindow>::vals =
126 {"clean_window", 0x024, 1010, {P, P, H}};
127
128template<> SparcFaultBase::FaultVals
129 SparcFault<DivisionByZero>::vals =
130 {"division_by_zero", 0x028, 1500, {P, P, H}};
131
132template<> SparcFaultBase::FaultVals
133 SparcFault<InternalProcessorError>::vals =
134 {"internal_processor_error", 0x029, 4, {H, H, H}};
135
136template<> SparcFaultBase::FaultVals
137 SparcFault<InstructionInvalidTSBEntry>::vals =
138 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}};
139
140template<> SparcFaultBase::FaultVals
141 SparcFault<DataInvalidTSBEntry>::vals =
142 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}};
143
144template<> SparcFaultBase::FaultVals
145 SparcFault<DataAccessException>::vals =
146 {"data_access_exception", 0x030, 1201, {H, H, H}};
147
148//XXX This trap is apparently dropped from ua2005
149/*template<> SparcFaultBase::FaultVals
150 SparcFault<DataAccessMMUMiss>::vals =
151 {"data_mmu", 0x031, 12, {H, H, H}};*/
152
153template<> SparcFaultBase::FaultVals
154 SparcFault<DataAccessError>::vals =
155 {"data_access_error", 0x032, 1210, {H, H, H}};
156
157template<> SparcFaultBase::FaultVals
158 SparcFault<DataAccessProtection>::vals =
159 {"data_access_protection", 0x033, 1207, {H, H, H}};
160
161template<> SparcFaultBase::FaultVals
162 SparcFault<MemAddressNotAligned>::vals =
163 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}};
164
165template<> SparcFaultBase::FaultVals
166 SparcFault<LDDFMemAddressNotAligned>::vals =
167 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}};
168
169template<> SparcFaultBase::FaultVals
170 SparcFault<STDFMemAddressNotAligned>::vals =
171 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}};
172
173template<> SparcFaultBase::FaultVals
174 SparcFault<PrivilegedAction>::vals =
175 {"privileged_action", 0x037, 1110, {H, H, SH}};
176
177template<> SparcFaultBase::FaultVals
178 SparcFault<LDQFMemAddressNotAligned>::vals =
179 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}};
180
181template<> SparcFaultBase::FaultVals
182 SparcFault<STQFMemAddressNotAligned>::vals =
183 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}};
184
185template<> SparcFaultBase::FaultVals
186 SparcFault<InstructionRealTranslationMiss>::vals =
187 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}};
188
189template<> SparcFaultBase::FaultVals
190 SparcFault<DataRealTranslationMiss>::vals =
191 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}};
192
193//XXX This trap is apparently dropped from ua2005
194/*template<> SparcFaultBase::FaultVals
195 SparcFault<AsyncDataError>::vals =
196 {"async_data", 0x040, 2, {H, H, H}};*/
197
198template<> SparcFaultBase::FaultVals
199 SparcFault<InterruptLevelN>::vals =
200 {"interrupt_level_n", 0x040, 0, {P, P, SH}};
201
202template<> SparcFaultBase::FaultVals
203 SparcFault<HstickMatch>::vals =
204 {"hstick_match", 0x05E, 1601, {H, H, H}};
205
206template<> SparcFaultBase::FaultVals
207 SparcFault<TrapLevelZero>::vals =
208 {"trap_level_zero", 0x05F, 202, {H, H, SH}};
209
210template<> SparcFaultBase::FaultVals
211 SparcFault<PAWatchpoint>::vals =
212 {"PA_watchpoint", 0x061, 1209, {H, H, H}};
213
214template<> SparcFaultBase::FaultVals
215 SparcFault<VAWatchpoint>::vals =
216 {"VA_watchpoint", 0x062, 1120, {P, P, SH}};
217
218template<> SparcFaultBase::FaultVals
219 SparcFault<FastInstructionAccessMMUMiss>::vals =
220 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}};
221
222template<> SparcFaultBase::FaultVals
223 SparcFault<FastDataAccessMMUMiss>::vals =
224 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}};
225
226template<> SparcFaultBase::FaultVals
227 SparcFault<FastDataAccessProtection>::vals =
228 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}};
229
230template<> SparcFaultBase::FaultVals
231 SparcFault<InstructionBreakpoint>::vals =
232 {"instruction_break", 0x076, 610, {H, H, H}};
233
234template<> SparcFaultBase::FaultVals
235 SparcFault<CpuMondo>::vals =
236 {"cpu_mondo", 0x07C, 1608, {P, P, SH}};
237
238template<> SparcFaultBase::FaultVals
239 SparcFault<DevMondo>::vals =
240 {"dev_mondo", 0x07D, 1611, {P, P, SH}};
241
242template<> SparcFaultBase::FaultVals
243 SparcFault<ResumableError>::vals =
244 {"resume_error", 0x07E, 3330, {P, P, SH}};
245
246template<> SparcFaultBase::FaultVals
247 SparcFault<SpillNNormal>::vals =
248 {"spill_n_normal", 0x080, 900, {P, P, H}};
249
250template<> SparcFaultBase::FaultVals
251 SparcFault<SpillNOther>::vals =
252 {"spill_n_other", 0x0A0, 900, {P, P, H}};
253
254template<> SparcFaultBase::FaultVals
255 SparcFault<FillNNormal>::vals =
256 {"fill_n_normal", 0x0C0, 900, {P, P, H}};
257
258template<> SparcFaultBase::FaultVals
259 SparcFault<FillNOther>::vals =
260 {"fill_n_other", 0x0E0, 900, {P, P, H}};
261
262template<> SparcFaultBase::FaultVals
263 SparcFault<TrapInstruction>::vals =
264 {"trap_instruction", 0x100, 1602, {P, P, H}};
265
266#if !FULL_SYSTEM
267template<> SparcFaultBase::FaultVals
268 SparcFault<PageTableFault>::vals =
269 {"page_table_fault", 0x0000, 0, {SH, SH, SH}};
270#endif
271
272/**
273 * This causes the thread context to enter RED state. This causes the side
274 * effects which go with entering RED state because of a trap.
275 */
276
277void enterREDState(ThreadContext *tc)
278{
279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282 //HPSTATE.red = 1
283 HPSTATE |= (1 << 5);
284 //HPSTATE.hpriv = 1
285 HPSTATE |= (1 << 2);
286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
288 //Legion sets it to 1.
289 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
290 PSTATE |= (1 << 2);
291 tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
292}
293
294/**
295 * This sets everything up for a RED state trap except for actually jumping to
296 * the handler.
297 */
298
299void doREDFault(ThreadContext *tc, TrapType tt)
300{
301 MiscReg TL = tc->readMiscReg(MISCREG_TL);
302 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
303 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
304 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
305 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
306 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
307 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
308 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
309 MiscReg GL = tc->readMiscReg(MISCREG_GL);
310 MiscReg PC = tc->readPC();
311 MiscReg NPC = tc->readNextPC();
312
313 TL++;
314
315 //set TSTATE.gl to gl
316 replaceBits(TSTATE, 42, 40, GL);
317 //set TSTATE.ccr to ccr
318 replaceBits(TSTATE, 39, 32, CCR);
319 //set TSTATE.asi to asi
320 replaceBits(TSTATE, 31, 24, ASI);
321 //set TSTATE.pstate to pstate
322 replaceBits(TSTATE, 20, 8, PSTATE);
323 //set TSTATE.cwp to cwp
324 replaceBits(TSTATE, 4, 0, CWP);
325
326 //Write back TSTATE
327 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
328
329 //set TPC to PC
330 tc->setMiscReg(MISCREG_TPC, PC);
331 //set TNPC to NPC
332 tc->setMiscReg(MISCREG_TNPC, NPC);
333
334 //set HTSTATE.hpstate to hpstate
335 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
336
337 //TT = trap type;
338 tc->setMiscReg(MISCREG_TT, tt);
339
340 //Update GL
341 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
342
343 //set PSTATE.mm to 00
344 //set PSTATE.pef to 1
345 PSTATE |= (1 << 4);
346 //set PSTATE.am to 0
347 PSTATE &= ~(1 << 3);
348/* //set PSTATE.priv to 0
349 PSTATE &= ~(1 << 2);*/
350 //set PSTATE.ie to 0
351 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
352 //Legion sets it to 1.
353 PSTATE |= (1 << 2);
354 //set PSTATE.cle to 0
355 PSTATE &= ~(1 << 9);
356 //PSTATE.tle is unchanged
357 //XXX Where is the tct bit?
358 //set PSTATE.tct to 0
343 PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
344 PSTATE |= (1 << 4); //set PSTATE.pef to 1
359 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
360
361 //set HPSTATE.red to 1
362 HPSTATE |= (1 << 5);
363 //set HPSTATE.hpriv to 1
364 HPSTATE |= (1 << 2);
365 //set HPSTATE.ibe to 0
366 HPSTATE &= ~(1 << 10);
367 //set HPSTATE.tlz to 0
368 HPSTATE &= ~(1 << 0);
369 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
370
371 bool changedCWP = true;
372 if(tt == 0x24)
373 CWP++;
374 else if(0x80 <= tt && tt <= 0xbf)
375 CWP += (CANSAVE + 2);
376 else if(0xc0 <= tt && tt <= 0xff)
377 CWP--;
378 else
379 changedCWP = false;
380
381 if(changedCWP)
382 {
383 CWP = (CWP + NWindows) % NWindows;
384 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
385 }
386}
387
388/**
389 * This sets everything up for a normal trap except for actually jumping to
390 * the handler.
391 */
392
393void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
394{
395 MiscReg TL = tc->readMiscReg(MISCREG_TL);
396 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
397 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
398 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
399 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
400 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
401 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
402 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
403 MiscReg GL = tc->readMiscReg(MISCREG_GL);
404 MiscReg PC = tc->readPC();
405 MiscReg NPC = tc->readNextPC();
406
407 //Increment the trap level
408 TL++;
409 tc->setMiscReg(MISCREG_TL, TL);
410
411 //Save off state
412
413 //set TSTATE.gl to gl
414 replaceBits(TSTATE, 42, 40, GL);
415 //set TSTATE.ccr to ccr
416 replaceBits(TSTATE, 39, 32, CCR);
417 //set TSTATE.asi to asi
418 replaceBits(TSTATE, 31, 24, ASI);
419 //set TSTATE.pstate to pstate
420 replaceBits(TSTATE, 20, 8, PSTATE);
421 //set TSTATE.cwp to cwp
422 replaceBits(TSTATE, 4, 0, CWP);
423
424 //Write back TSTATE
425 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
426
427 //set TPC to PC
428 tc->setMiscReg(MISCREG_TPC, PC);
429 //set TNPC to NPC
430 tc->setMiscReg(MISCREG_TNPC, NPC);
431
432 //set HTSTATE.hpstate to hpstate
433 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
434
435 //TT = trap type;
436 tc->setMiscReg(MISCREG_TT, tt);
437
438 //Update the global register level
439 if (!gotoHpriv)
440 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
441 else
442 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
443
444 //PSTATE.mm is unchanged
345 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
346
347 //set HPSTATE.red to 1
348 HPSTATE |= (1 << 5);
349 //set HPSTATE.hpriv to 1
350 HPSTATE |= (1 << 2);
351 //set HPSTATE.ibe to 0
352 HPSTATE &= ~(1 << 10);
353 //set HPSTATE.tlz to 0
354 HPSTATE &= ~(1 << 0);
355 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
356
357 bool changedCWP = true;
358 if(tt == 0x24)
359 CWP++;
360 else if(0x80 <= tt && tt <= 0xbf)
361 CWP += (CANSAVE + 2);
362 else if(0xc0 <= tt && tt <= 0xff)
363 CWP--;
364 else
365 changedCWP = false;
366
367 if(changedCWP)
368 {
369 CWP = (CWP + NWindows) % NWindows;
370 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
371 }
372}
373
374/**
375 * This sets everything up for a normal trap except for actually jumping to
376 * the handler.
377 */
378
379void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
380{
381 MiscReg TL = tc->readMiscReg(MISCREG_TL);
382 MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
383 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
384 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
385 MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
386 MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
387 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
388 MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
389 MiscReg GL = tc->readMiscReg(MISCREG_GL);
390 MiscReg PC = tc->readPC();
391 MiscReg NPC = tc->readNextPC();
392
393 //Increment the trap level
394 TL++;
395 tc->setMiscReg(MISCREG_TL, TL);
396
397 //Save off state
398
399 //set TSTATE.gl to gl
400 replaceBits(TSTATE, 42, 40, GL);
401 //set TSTATE.ccr to ccr
402 replaceBits(TSTATE, 39, 32, CCR);
403 //set TSTATE.asi to asi
404 replaceBits(TSTATE, 31, 24, ASI);
405 //set TSTATE.pstate to pstate
406 replaceBits(TSTATE, 20, 8, PSTATE);
407 //set TSTATE.cwp to cwp
408 replaceBits(TSTATE, 4, 0, CWP);
409
410 //Write back TSTATE
411 tc->setMiscReg(MISCREG_TSTATE, TSTATE);
412
413 //set TPC to PC
414 tc->setMiscReg(MISCREG_TPC, PC);
415 //set TNPC to NPC
416 tc->setMiscReg(MISCREG_TNPC, NPC);
417
418 //set HTSTATE.hpstate to hpstate
419 tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
420
421 //TT = trap type;
422 tc->setMiscReg(MISCREG_TT, tt);
423
424 //Update the global register level
425 if (!gotoHpriv)
426 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
427 else
428 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
429
430 //PSTATE.mm is unchanged
445 //PSTATE.pef = whether or not an fpu is present
446 //XXX We'll say there's one present, even though there aren't
447 //implementations for a decent number of the instructions
448 PSTATE |= (1 << 4);
449 //PSTATE.am = 0
450 PSTATE &= ~(1 << 3);
451 if (!gotoHpriv)
452 {
453 //PSTATE.priv = 1
454 PSTATE |= (1 << 2);
455 //PSTATE.cle = PSTATE.tle
456 replaceBits(PSTATE, 9, 9, PSTATE >> 8);
457 }
458 else
459 {
460 //PSTATE.priv = 0
461 //PSTATE.priv is set to 1 here. The manual says it should be 0, but
462 //Legion sets it to 1.
463 PSTATE |= (1 << 2);
464 //PSTATE.cle = 0
465 PSTATE &= ~(1 << 9);
466 }
467 //PSTATE.ie = 0
468 PSTATE &= ~(1 << 1);
431 PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
432 PSTATE &= ~(1 << 3); //PSTATE.am = 0
433 PSTATE &= ~(1 << 1); //PSTATE.ie = 0
469 //PSTATE.tle is unchanged
470 //PSTATE.tct = 0
434 //PSTATE.tle is unchanged
435 //PSTATE.tct = 0
471 //XXX Where exactly is this field?
472 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
473
474 if (gotoHpriv)
475 {
436
437 if (gotoHpriv)
438 {
476 //HPSTATE.red = 0
477 HPSTATE &= ~(1 << 5);
478 //HPSTATE.hpriv = 1
479 HPSTATE |= (1 << 2);
480 //HPSTATE.ibe = 0
481 HPSTATE &= ~(1 << 10);
439 PSTATE &= ~(1 << 9); // PSTATE.cle = 0
440 //The manual says PSTATE.priv should be 0, but Legion leaves it alone
441 HPSTATE &= ~(1 << 5); //HPSTATE.red = 0
442 HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
443 HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
482 //HPSTATE.tlz is unchanged
483 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
444 //HPSTATE.tlz is unchanged
445 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
446 } else { // we are going to priv
447 PSTATE |= (1 << 2); //PSTATE.priv = 1
448 replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
484 }
449 }
450 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
485
451
452
486 bool changedCWP = true;
487 if (tt == 0x24)
488 CWP++;
489 else if (0x80 <= tt && tt <= 0xbf)
490 CWP += (CANSAVE + 2);
491 else if (0xc0 <= tt && tt <= 0xff)
492 CWP--;
493 else
494 changedCWP = false;
495
496 if (changedCWP)
497 {
498 CWP = (CWP + NWindows) % NWindows;
499 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
500 }
501}
502
503void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
504{
505 //XXX The following constant might belong in a header file.
506 const Addr RSTVAddr = 0xFFF0000000ULL;
507 PC = RSTVAddr | ((TT << 5) & 0xFF);
508 NPC = PC + sizeof(MachInst);
509}
510
511void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
512{
513 Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
514 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
515 NPC = PC + sizeof(MachInst);
516}
517
518void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
519{
520 Addr TBA = tc->readMiscReg(MISCREG_TBA);
521 PC = (TBA & ~mask(15)) |
522 (TL > 1 ? (1 << 14) : 0) |
523 ((TT << 5) & mask(14));
524 NPC = PC + sizeof(MachInst);
525}
526
527#if FULL_SYSTEM
528
529void SparcFaultBase::invoke(ThreadContext * tc)
530{
531 //panic("Invoking a second fault!\n");
532 FaultBase::invoke(tc);
533 countStat()++;
534
535 //We can refer to this to see what the trap level -was-, but something
536 //in the middle could change it in the regfile out from under us.
537 MiscReg tl = tc->readMiscReg(MISCREG_TL);
538 MiscReg tt = tc->readMiscReg(MISCREG_TT);
539 MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
540 MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
541
542 Addr PC, NPC;
543
544 PrivilegeLevel current;
545 if (hpstate & HPSTATE::hpriv)
546 current = Hyperprivileged;
547 else if (pstate & PSTATE::priv)
548 current = Privileged;
549 else
550 current = User;
551
552 PrivilegeLevel level = getNextLevel(current);
553
554 if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
555 getREDVector(5, PC, NPC);
556 doREDFault(tc, tt);
557 //This changes the hpstate and pstate, so we need to make sure we
558 //save the old version on the trap stack in doREDFault.
559 enterREDState(tc);
560 } else if (tl == MaxTL) {
561 panic("Should go to error state here.. crap\n");
562 //Do error_state somehow?
563 //Probably inject a WDR fault using the interrupt mechanism.
564 //What should the PC and NPC be set to?
565 } else if (tl > MaxPTL && level == Privileged) {
566 //guest_watchdog fault
567 doNormalFault(tc, trapType(), true);
568 getHyperVector(tc, PC, NPC, 2);
569 } else if (level == Hyperprivileged ||
570 level == Privileged && trapType() >= 384) {
571 doNormalFault(tc, trapType(), true);
572 getHyperVector(tc, PC, NPC, trapType());
573 } else {
574 doNormalFault(tc, trapType(), false);
575 getPrivVector(tc, PC, NPC, trapType(), tl+1);
576 }
577
578 tc->setPC(PC);
579 tc->setNextPC(NPC);
580 tc->setNextNPC(NPC + sizeof(MachInst));
581}
582
583void PowerOnReset::invoke(ThreadContext * tc)
584{
585 //For SPARC, when a system is first started, there is a power
586 //on reset Trap which sets the processor into the following state.
587 //Bits that aren't set aren't defined on startup.
588
589 tc->setMiscReg(MISCREG_TL, MaxTL);
590 tc->setMiscReg(MISCREG_TT, trapType());
591 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
592
593 //Turn on pef and priv, set everything else to 0
594 tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
595
596 //Turn on red and hpriv, set everything else to 0
597 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
598 //HPSTATE.red = 1
599 HPSTATE |= (1 << 5);
600 //HPSTATE.hpriv = 1
601 HPSTATE |= (1 << 2);
602 //HPSTATE.ibe = 0
603 HPSTATE &= ~(1 << 10);
604 //HPSTATE.tlz = 0
605 HPSTATE &= ~(1 << 0);
606 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
607
608 //The tick register is unreadable by nonprivileged software
609 tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
610
611 //Enter RED state. We do this last so that the actual state preserved in
612 //the trap stack is the state from before this fault.
613 enterREDState(tc);
614
615 Addr PC, NPC;
616 getREDVector(trapType(), PC, NPC);
617 tc->setPC(PC);
618 tc->setNextPC(NPC);
619 tc->setNextNPC(NPC + sizeof(MachInst));
620
621 //These registers are specified as "undefined" after a POR, and they
622 //should have reasonable values after the miscregfile is reset
623 /*
624 // Clear all the soft interrupt bits
625 softint = 0;
626 // disable timer compare interrupts, reset tick_cmpr
627 tc->setMiscReg(MISCREG_
628 tick_cmprFields.int_dis = 1;
629 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
630 stickFields.npt = 1; //The TICK register is unreadable by by !priv
631 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
632 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
633
634 tt[tl] = _trapType;
635
636 hintp = 0; // no interrupts pending
637 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
638 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
639 */
640}
641
642#else // !FULL_SYSTEM
643
644void SpillNNormal::invoke(ThreadContext *tc)
645{
646 doNormalFault(tc, trapType(), false);
647
648 Process *p = tc->getProcessPtr();
649
650 //XXX This will only work in faults from a SparcLiveProcess
651 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
652 assert(lp);
653
654 //Then adjust the PC and NPC
655 Addr spillStart = lp->readSpillStart();
656 tc->setPC(spillStart);
657 tc->setNextPC(spillStart + sizeof(MachInst));
658 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
659}
660
661void FillNNormal::invoke(ThreadContext *tc)
662{
663 doNormalFault(tc, trapType(), false);
664
665 Process * p = tc->getProcessPtr();
666
667 //XXX This will only work in faults from a SparcLiveProcess
668 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
669 assert(lp);
670
671 //Then adjust the PC and NPC
672 Addr fillStart = lp->readFillStart();
673 tc->setPC(fillStart);
674 tc->setNextPC(fillStart + sizeof(MachInst));
675 tc->setNextNPC(fillStart + 2*sizeof(MachInst));
676}
677
678void PageTableFault::invoke(ThreadContext *tc)
679{
680 Process *p = tc->getProcessPtr();
681
682 // address is higher than the stack region or in the current stack region
683 if (vaddr > p->stack_base || vaddr > p->stack_min)
684 FaultBase::invoke(tc);
685
686 // We've accessed the next page
687 if (vaddr > p->stack_min - PageBytes) {
688 p->stack_min -= PageBytes;
689 if (p->stack_base - p->stack_min > 8*1024*1024)
690 fatal("Over max stack size for one thread\n");
691 p->pTable->allocate(p->stack_min, PageBytes);
692 warn("Increasing stack size by one page.");
693 } else {
694 FaultBase::invoke(tc);
695 }
696}
697
698#endif
699
700} // namespace SparcISA
701
453 bool changedCWP = true;
454 if (tt == 0x24)
455 CWP++;
456 else if (0x80 <= tt && tt <= 0xbf)
457 CWP += (CANSAVE + 2);
458 else if (0xc0 <= tt && tt <= 0xff)
459 CWP--;
460 else
461 changedCWP = false;
462
463 if (changedCWP)
464 {
465 CWP = (CWP + NWindows) % NWindows;
466 tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
467 }
468}
469
470void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
471{
472 //XXX The following constant might belong in a header file.
473 const Addr RSTVAddr = 0xFFF0000000ULL;
474 PC = RSTVAddr | ((TT << 5) & 0xFF);
475 NPC = PC + sizeof(MachInst);
476}
477
478void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
479{
480 Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
481 PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
482 NPC = PC + sizeof(MachInst);
483}
484
485void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
486{
487 Addr TBA = tc->readMiscReg(MISCREG_TBA);
488 PC = (TBA & ~mask(15)) |
489 (TL > 1 ? (1 << 14) : 0) |
490 ((TT << 5) & mask(14));
491 NPC = PC + sizeof(MachInst);
492}
493
494#if FULL_SYSTEM
495
496void SparcFaultBase::invoke(ThreadContext * tc)
497{
498 //panic("Invoking a second fault!\n");
499 FaultBase::invoke(tc);
500 countStat()++;
501
502 //We can refer to this to see what the trap level -was-, but something
503 //in the middle could change it in the regfile out from under us.
504 MiscReg tl = tc->readMiscReg(MISCREG_TL);
505 MiscReg tt = tc->readMiscReg(MISCREG_TT);
506 MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
507 MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
508
509 Addr PC, NPC;
510
511 PrivilegeLevel current;
512 if (hpstate & HPSTATE::hpriv)
513 current = Hyperprivileged;
514 else if (pstate & PSTATE::priv)
515 current = Privileged;
516 else
517 current = User;
518
519 PrivilegeLevel level = getNextLevel(current);
520
521 if ((hpstate & HPSTATE::red) || (tl == MaxTL - 1)) {
522 getREDVector(5, PC, NPC);
523 doREDFault(tc, tt);
524 //This changes the hpstate and pstate, so we need to make sure we
525 //save the old version on the trap stack in doREDFault.
526 enterREDState(tc);
527 } else if (tl == MaxTL) {
528 panic("Should go to error state here.. crap\n");
529 //Do error_state somehow?
530 //Probably inject a WDR fault using the interrupt mechanism.
531 //What should the PC and NPC be set to?
532 } else if (tl > MaxPTL && level == Privileged) {
533 //guest_watchdog fault
534 doNormalFault(tc, trapType(), true);
535 getHyperVector(tc, PC, NPC, 2);
536 } else if (level == Hyperprivileged ||
537 level == Privileged && trapType() >= 384) {
538 doNormalFault(tc, trapType(), true);
539 getHyperVector(tc, PC, NPC, trapType());
540 } else {
541 doNormalFault(tc, trapType(), false);
542 getPrivVector(tc, PC, NPC, trapType(), tl+1);
543 }
544
545 tc->setPC(PC);
546 tc->setNextPC(NPC);
547 tc->setNextNPC(NPC + sizeof(MachInst));
548}
549
550void PowerOnReset::invoke(ThreadContext * tc)
551{
552 //For SPARC, when a system is first started, there is a power
553 //on reset Trap which sets the processor into the following state.
554 //Bits that aren't set aren't defined on startup.
555
556 tc->setMiscReg(MISCREG_TL, MaxTL);
557 tc->setMiscReg(MISCREG_TT, trapType());
558 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
559
560 //Turn on pef and priv, set everything else to 0
561 tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
562
563 //Turn on red and hpriv, set everything else to 0
564 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
565 //HPSTATE.red = 1
566 HPSTATE |= (1 << 5);
567 //HPSTATE.hpriv = 1
568 HPSTATE |= (1 << 2);
569 //HPSTATE.ibe = 0
570 HPSTATE &= ~(1 << 10);
571 //HPSTATE.tlz = 0
572 HPSTATE &= ~(1 << 0);
573 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
574
575 //The tick register is unreadable by nonprivileged software
576 tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
577
578 //Enter RED state. We do this last so that the actual state preserved in
579 //the trap stack is the state from before this fault.
580 enterREDState(tc);
581
582 Addr PC, NPC;
583 getREDVector(trapType(), PC, NPC);
584 tc->setPC(PC);
585 tc->setNextPC(NPC);
586 tc->setNextNPC(NPC + sizeof(MachInst));
587
588 //These registers are specified as "undefined" after a POR, and they
589 //should have reasonable values after the miscregfile is reset
590 /*
591 // Clear all the soft interrupt bits
592 softint = 0;
593 // disable timer compare interrupts, reset tick_cmpr
594 tc->setMiscReg(MISCREG_
595 tick_cmprFields.int_dis = 1;
596 tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
597 stickFields.npt = 1; //The TICK register is unreadable by by !priv
598 stick_cmprFields.int_dis = 1; // disable timer compare interrupts
599 stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
600
601 tt[tl] = _trapType;
602
603 hintp = 0; // no interrupts pending
604 hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
605 hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
606 */
607}
608
609#else // !FULL_SYSTEM
610
611void SpillNNormal::invoke(ThreadContext *tc)
612{
613 doNormalFault(tc, trapType(), false);
614
615 Process *p = tc->getProcessPtr();
616
617 //XXX This will only work in faults from a SparcLiveProcess
618 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
619 assert(lp);
620
621 //Then adjust the PC and NPC
622 Addr spillStart = lp->readSpillStart();
623 tc->setPC(spillStart);
624 tc->setNextPC(spillStart + sizeof(MachInst));
625 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
626}
627
628void FillNNormal::invoke(ThreadContext *tc)
629{
630 doNormalFault(tc, trapType(), false);
631
632 Process * p = tc->getProcessPtr();
633
634 //XXX This will only work in faults from a SparcLiveProcess
635 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
636 assert(lp);
637
638 //Then adjust the PC and NPC
639 Addr fillStart = lp->readFillStart();
640 tc->setPC(fillStart);
641 tc->setNextPC(fillStart + sizeof(MachInst));
642 tc->setNextNPC(fillStart + 2*sizeof(MachInst));
643}
644
645void PageTableFault::invoke(ThreadContext *tc)
646{
647 Process *p = tc->getProcessPtr();
648
649 // address is higher than the stack region or in the current stack region
650 if (vaddr > p->stack_base || vaddr > p->stack_min)
651 FaultBase::invoke(tc);
652
653 // We've accessed the next page
654 if (vaddr > p->stack_min - PageBytes) {
655 p->stack_min -= PageBytes;
656 if (p->stack_base - p->stack_min > 8*1024*1024)
657 fatal("Over max stack size for one thread\n");
658 p->pTable->allocate(p->stack_min, PageBytes);
659 warn("Increasing stack size by one page.");
660 } else {
661 FaultBase::invoke(tc);
662 }
663}
664
665#endif
666
667} // namespace SparcISA
668