faults.cc (8829:d21889bface6) | faults.cc (9551:f867e530f39b) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 37 unchanged lines hidden (view full) --- 46 47using namespace std; 48 49namespace SparcISA 50{ 51 52template<> SparcFaultBase::FaultVals 53 SparcFault<PowerOnReset>::vals = | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 37 unchanged lines hidden (view full) --- 46 47using namespace std; 48 49namespace SparcISA 50{ 51 52template<> SparcFaultBase::FaultVals 53 SparcFault<PowerOnReset>::vals = |
54 {"power_on_reset", 0x001, 0, {H, H, H}}; | 54{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()}; |
55 56template<> SparcFaultBase::FaultVals 57 SparcFault<WatchDogReset>::vals = | 55 56template<> SparcFaultBase::FaultVals 57 SparcFault<WatchDogReset>::vals = |
58 {"watch_dog_reset", 0x002, 120, {H, H, H}}; | 58{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()}; |
59 60template<> SparcFaultBase::FaultVals 61 SparcFault<ExternallyInitiatedReset>::vals = | 59 60template<> SparcFaultBase::FaultVals 61 SparcFault<ExternallyInitiatedReset>::vals = |
62 {"externally_initiated_reset", 0x003, 110, {H, H, H}}; | 62{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()}; |
63 64template<> SparcFaultBase::FaultVals 65 SparcFault<SoftwareInitiatedReset>::vals = | 63 64template<> SparcFaultBase::FaultVals 65 SparcFault<SoftwareInitiatedReset>::vals = |
66 {"software_initiated_reset", 0x004, 130, {SH, SH, H}}; | 66{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()}; |
67 68template<> SparcFaultBase::FaultVals 69 SparcFault<REDStateException>::vals = | 67 68template<> SparcFaultBase::FaultVals 69 SparcFault<REDStateException>::vals = |
70 {"RED_state_exception", 0x005, 1, {H, H, H}}; | 70{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()}; |
71 72template<> SparcFaultBase::FaultVals 73 SparcFault<StoreError>::vals = | 71 72template<> SparcFaultBase::FaultVals 73 SparcFault<StoreError>::vals = |
74 {"store_error", 0x007, 201, {H, H, H}}; | 74{"store_error", 0x007, 201, {H, H, H}, FaultStat()}; |
75 76template<> SparcFaultBase::FaultVals 77 SparcFault<InstructionAccessException>::vals = | 75 76template<> SparcFaultBase::FaultVals 77 SparcFault<InstructionAccessException>::vals = |
78 {"instruction_access_exception", 0x008, 300, {H, H, H}}; | 78{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()}; |
79 80//XXX This trap is apparently dropped from ua2005 81/*template<> SparcFaultBase::FaultVals 82 SparcFault<InstructionAccessMMUMiss>::vals = 83 {"inst_mmu", 0x009, 2, {H, H, H}};*/ 84 85template<> SparcFaultBase::FaultVals 86 SparcFault<InstructionAccessError>::vals = | 79 80//XXX This trap is apparently dropped from ua2005 81/*template<> SparcFaultBase::FaultVals 82 SparcFault<InstructionAccessMMUMiss>::vals = 83 {"inst_mmu", 0x009, 2, {H, H, H}};*/ 84 85template<> SparcFaultBase::FaultVals 86 SparcFault<InstructionAccessError>::vals = |
87 {"instruction_access_error", 0x00A, 400, {H, H, H}}; | 87{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()}; |
88 89template<> SparcFaultBase::FaultVals 90 SparcFault<IllegalInstruction>::vals = | 88 89template<> SparcFaultBase::FaultVals 90 SparcFault<IllegalInstruction>::vals = |
91 {"illegal_instruction", 0x010, 620, {H, H, H}}; | 91{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()}; |
92 93template<> SparcFaultBase::FaultVals 94 SparcFault<PrivilegedOpcode>::vals = | 92 93template<> SparcFaultBase::FaultVals 94 SparcFault<PrivilegedOpcode>::vals = |
95 {"privileged_opcode", 0x011, 700, {P, SH, SH}}; | 95{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()}; |
96 97//XXX This trap is apparently dropped from ua2005 98/*template<> SparcFaultBase::FaultVals 99 SparcFault<UnimplementedLDD>::vals = 100 {"unimp_ldd", 0x012, 6, {H, H, H}};*/ 101 102//XXX This trap is apparently dropped from ua2005 103/*template<> SparcFaultBase::FaultVals 104 SparcFault<UnimplementedSTD>::vals = 105 {"unimp_std", 0x013, 6, {H, H, H}};*/ 106 107template<> SparcFaultBase::FaultVals 108 SparcFault<FpDisabled>::vals = | 96 97//XXX This trap is apparently dropped from ua2005 98/*template<> SparcFaultBase::FaultVals 99 SparcFault<UnimplementedLDD>::vals = 100 {"unimp_ldd", 0x012, 6, {H, H, H}};*/ 101 102//XXX This trap is apparently dropped from ua2005 103/*template<> SparcFaultBase::FaultVals 104 SparcFault<UnimplementedSTD>::vals = 105 {"unimp_std", 0x013, 6, {H, H, H}};*/ 106 107template<> SparcFaultBase::FaultVals 108 SparcFault<FpDisabled>::vals = |
109 {"fp_disabled", 0x020, 800, {P, P, H}}; | 109{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()}; |
110 111template<> SparcFaultBase::FaultVals 112 SparcFault<FpExceptionIEEE754>::vals = | 110 111template<> SparcFaultBase::FaultVals 112 SparcFault<FpExceptionIEEE754>::vals = |
113 {"fp_exception_ieee_754", 0x021, 1110, {P, P, H}}; | 113{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()}; |
114 115template<> SparcFaultBase::FaultVals 116 SparcFault<FpExceptionOther>::vals = | 114 115template<> SparcFaultBase::FaultVals 116 SparcFault<FpExceptionOther>::vals = |
117 {"fp_exception_other", 0x022, 1110, {P, P, H}}; | 117{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()}; |
118 119template<> SparcFaultBase::FaultVals 120 SparcFault<TagOverflow>::vals = | 118 119template<> SparcFaultBase::FaultVals 120 SparcFault<TagOverflow>::vals = |
121 {"tag_overflow", 0x023, 1400, {P, P, H}}; | 121{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()}; |
122 123template<> SparcFaultBase::FaultVals 124 SparcFault<CleanWindow>::vals = | 122 123template<> SparcFaultBase::FaultVals 124 SparcFault<CleanWindow>::vals = |
125 {"clean_window", 0x024, 1010, {P, P, H}}; | 125{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()}; |
126 127template<> SparcFaultBase::FaultVals 128 SparcFault<DivisionByZero>::vals = | 126 127template<> SparcFaultBase::FaultVals 128 SparcFault<DivisionByZero>::vals = |
129 {"division_by_zero", 0x028, 1500, {P, P, H}}; | 129{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()}; |
130 131template<> SparcFaultBase::FaultVals 132 SparcFault<InternalProcessorError>::vals = | 130 131template<> SparcFaultBase::FaultVals 132 SparcFault<InternalProcessorError>::vals = |
133 {"internal_processor_error", 0x029, 4, {H, H, H}}; | 133{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()}; |
134 135template<> SparcFaultBase::FaultVals 136 SparcFault<InstructionInvalidTSBEntry>::vals = | 134 135template<> SparcFaultBase::FaultVals 136 SparcFault<InstructionInvalidTSBEntry>::vals = |
137 {"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}}; | 137{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()}; |
138 139template<> SparcFaultBase::FaultVals 140 SparcFault<DataInvalidTSBEntry>::vals = | 138 139template<> SparcFaultBase::FaultVals 140 SparcFault<DataInvalidTSBEntry>::vals = |
141 {"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}}; | 141{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()}; |
142 143template<> SparcFaultBase::FaultVals 144 SparcFault<DataAccessException>::vals = | 142 143template<> SparcFaultBase::FaultVals 144 SparcFault<DataAccessException>::vals = |
145 {"data_access_exception", 0x030, 1201, {H, H, H}}; | 145{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()}; |
146 147//XXX This trap is apparently dropped from ua2005 148/*template<> SparcFaultBase::FaultVals 149 SparcFault<DataAccessMMUMiss>::vals = 150 {"data_mmu", 0x031, 12, {H, H, H}};*/ 151 152template<> SparcFaultBase::FaultVals 153 SparcFault<DataAccessError>::vals = | 146 147//XXX This trap is apparently dropped from ua2005 148/*template<> SparcFaultBase::FaultVals 149 SparcFault<DataAccessMMUMiss>::vals = 150 {"data_mmu", 0x031, 12, {H, H, H}};*/ 151 152template<> SparcFaultBase::FaultVals 153 SparcFault<DataAccessError>::vals = |
154 {"data_access_error", 0x032, 1210, {H, H, H}}; | 154{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()}; |
155 156template<> SparcFaultBase::FaultVals 157 SparcFault<DataAccessProtection>::vals = | 155 156template<> SparcFaultBase::FaultVals 157 SparcFault<DataAccessProtection>::vals = |
158 {"data_access_protection", 0x033, 1207, {H, H, H}}; | 158{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()}; |
159 160template<> SparcFaultBase::FaultVals 161 SparcFault<MemAddressNotAligned>::vals = | 159 160template<> SparcFaultBase::FaultVals 161 SparcFault<MemAddressNotAligned>::vals = |
162 {"mem_address_not_aligned", 0x034, 1020, {H, H, H}}; | 162{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()}; |
163 164template<> SparcFaultBase::FaultVals 165 SparcFault<LDDFMemAddressNotAligned>::vals = | 163 164template<> SparcFaultBase::FaultVals 165 SparcFault<LDDFMemAddressNotAligned>::vals = |
166 {"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}}; | 166{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()}; |
167 168template<> SparcFaultBase::FaultVals 169 SparcFault<STDFMemAddressNotAligned>::vals = | 167 168template<> SparcFaultBase::FaultVals 169 SparcFault<STDFMemAddressNotAligned>::vals = |
170 {"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}}; | 170{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()}; |
171 172template<> SparcFaultBase::FaultVals 173 SparcFault<PrivilegedAction>::vals = | 171 172template<> SparcFaultBase::FaultVals 173 SparcFault<PrivilegedAction>::vals = |
174 {"privileged_action", 0x037, 1110, {H, H, SH}}; | 174{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()}; |
175 176template<> SparcFaultBase::FaultVals 177 SparcFault<LDQFMemAddressNotAligned>::vals = | 175 176template<> SparcFaultBase::FaultVals 177 SparcFault<LDQFMemAddressNotAligned>::vals = |
178 {"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}}; | 178{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()}; |
179 180template<> SparcFaultBase::FaultVals 181 SparcFault<STQFMemAddressNotAligned>::vals = | 179 180template<> SparcFaultBase::FaultVals 181 SparcFault<STQFMemAddressNotAligned>::vals = |
182 {"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}}; | 182{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()}; |
183 184template<> SparcFaultBase::FaultVals 185 SparcFault<InstructionRealTranslationMiss>::vals = | 183 184template<> SparcFaultBase::FaultVals 185 SparcFault<InstructionRealTranslationMiss>::vals = |
186 {"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}}; | 186{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()}; |
187 188template<> SparcFaultBase::FaultVals 189 SparcFault<DataRealTranslationMiss>::vals = | 187 188template<> SparcFaultBase::FaultVals 189 SparcFault<DataRealTranslationMiss>::vals = |
190 {"data_real_translation_miss", 0x03F, 1203, {H, H, H}}; | 190{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()}; |
191 192//XXX This trap is apparently dropped from ua2005 193/*template<> SparcFaultBase::FaultVals 194 SparcFault<AsyncDataError>::vals = 195 {"async_data", 0x040, 2, {H, H, H}};*/ 196 197template<> SparcFaultBase::FaultVals 198 SparcFault<InterruptLevelN>::vals = | 191 192//XXX This trap is apparently dropped from ua2005 193/*template<> SparcFaultBase::FaultVals 194 SparcFault<AsyncDataError>::vals = 195 {"async_data", 0x040, 2, {H, H, H}};*/ 196 197template<> SparcFaultBase::FaultVals 198 SparcFault<InterruptLevelN>::vals = |
199 {"interrupt_level_n", 0x040, 0, {P, P, SH}}; | 199{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()}; |
200 201template<> SparcFaultBase::FaultVals 202 SparcFault<HstickMatch>::vals = | 200 201template<> SparcFaultBase::FaultVals 202 SparcFault<HstickMatch>::vals = |
203 {"hstick_match", 0x05E, 1601, {H, H, H}}; | 203{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()}; |
204 205template<> SparcFaultBase::FaultVals 206 SparcFault<TrapLevelZero>::vals = | 204 205template<> SparcFaultBase::FaultVals 206 SparcFault<TrapLevelZero>::vals = |
207 {"trap_level_zero", 0x05F, 202, {H, H, SH}}; | 207{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()}; |
208 209template<> SparcFaultBase::FaultVals 210 SparcFault<InterruptVector>::vals = | 208 209template<> SparcFaultBase::FaultVals 210 SparcFault<InterruptVector>::vals = |
211 {"interrupt_vector", 0x060, 2630, {H, H, H}}; | 211{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()}; |
212 213template<> SparcFaultBase::FaultVals 214 SparcFault<PAWatchpoint>::vals = | 212 213template<> SparcFaultBase::FaultVals 214 SparcFault<PAWatchpoint>::vals = |
215 {"PA_watchpoint", 0x061, 1209, {H, H, H}}; | 215{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()}; |
216 217template<> SparcFaultBase::FaultVals 218 SparcFault<VAWatchpoint>::vals = | 216 217template<> SparcFaultBase::FaultVals 218 SparcFault<VAWatchpoint>::vals = |
219 {"VA_watchpoint", 0x062, 1120, {P, P, SH}}; | 219{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()}; |
220 221template<> SparcFaultBase::FaultVals 222 SparcFault<FastInstructionAccessMMUMiss>::vals = | 220 221template<> SparcFaultBase::FaultVals 222 SparcFault<FastInstructionAccessMMUMiss>::vals = |
223 {"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}}; | 223{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()}; |
224 225template<> SparcFaultBase::FaultVals 226 SparcFault<FastDataAccessMMUMiss>::vals = | 224 225template<> SparcFaultBase::FaultVals 226 SparcFault<FastDataAccessMMUMiss>::vals = |
227 {"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}}; | 227{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()}; |
228 229template<> SparcFaultBase::FaultVals 230 SparcFault<FastDataAccessProtection>::vals = | 228 229template<> SparcFaultBase::FaultVals 230 SparcFault<FastDataAccessProtection>::vals = |
231 {"fast_data_access_protection", 0x06C, 1207, {H, H, H}}; | 231{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()}; |
232 233template<> SparcFaultBase::FaultVals 234 SparcFault<InstructionBreakpoint>::vals = | 232 233template<> SparcFaultBase::FaultVals 234 SparcFault<InstructionBreakpoint>::vals = |
235 {"instruction_break", 0x076, 610, {H, H, H}}; | 235{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()}; |
236 237template<> SparcFaultBase::FaultVals 238 SparcFault<CpuMondo>::vals = | 236 237template<> SparcFaultBase::FaultVals 238 SparcFault<CpuMondo>::vals = |
239 {"cpu_mondo", 0x07C, 1608, {P, P, SH}}; | 239{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()}; |
240 241template<> SparcFaultBase::FaultVals 242 SparcFault<DevMondo>::vals = | 240 241template<> SparcFaultBase::FaultVals 242 SparcFault<DevMondo>::vals = |
243 {"dev_mondo", 0x07D, 1611, {P, P, SH}}; | 243{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()}; |
244 245template<> SparcFaultBase::FaultVals 246 SparcFault<ResumableError>::vals = | 244 245template<> SparcFaultBase::FaultVals 246 SparcFault<ResumableError>::vals = |
247 {"resume_error", 0x07E, 3330, {P, P, SH}}; | 247{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()}; |
248 249template<> SparcFaultBase::FaultVals 250 SparcFault<SpillNNormal>::vals = | 248 249template<> SparcFaultBase::FaultVals 250 SparcFault<SpillNNormal>::vals = |
251 {"spill_n_normal", 0x080, 900, {P, P, H}}; | 251{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()}; |
252 253template<> SparcFaultBase::FaultVals 254 SparcFault<SpillNOther>::vals = | 252 253template<> SparcFaultBase::FaultVals 254 SparcFault<SpillNOther>::vals = |
255 {"spill_n_other", 0x0A0, 900, {P, P, H}}; | 255{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()}; |
256 257template<> SparcFaultBase::FaultVals 258 SparcFault<FillNNormal>::vals = | 256 257template<> SparcFaultBase::FaultVals 258 SparcFault<FillNNormal>::vals = |
259 {"fill_n_normal", 0x0C0, 900, {P, P, H}}; | 259{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()}; |
260 261template<> SparcFaultBase::FaultVals 262 SparcFault<FillNOther>::vals = | 260 261template<> SparcFaultBase::FaultVals 262 SparcFault<FillNOther>::vals = |
263 {"fill_n_other", 0x0E0, 900, {P, P, H}}; | 263{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()}; |
264 265template<> SparcFaultBase::FaultVals 266 SparcFault<TrapInstruction>::vals = | 264 265template<> SparcFaultBase::FaultVals 266 SparcFault<TrapInstruction>::vals = |
267 {"trap_instruction", 0x100, 1602, {P, P, H}}; | 267{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()}; |
268 269/** 270 * This causes the thread context to enter RED state. This causes the side 271 * effects which go with entering RED state because of a trap. 272 */ 273 274void 275enterREDState(ThreadContext *tc) --- 452 unchanged lines hidden --- | 268 269/** 270 * This causes the thread context to enter RED state. This causes the side 271 * effects which go with entering RED state because of a trap. 272 */ 273 274void 275enterREDState(ThreadContext *tc) --- 452 unchanged lines hidden --- |