faults.cc (8767:e575781f71b8) | faults.cc (8778:fbaf6af0be93) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 * Kevin Lim 30 */ 31 32#include <algorithm> 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 * Kevin Lim 30 */ 31 32#include <algorithm> 33 34#include "arch/sparc/faults.hh" 35#include "arch/sparc/isa_traits.hh" |
36#include "arch/sparc/process.hh" |
|
36#include "arch/sparc/types.hh" 37#include "base/bitfield.hh" 38#include "base/trace.hh" 39#include "sim/full_system.hh" 40#include "cpu/base.hh" 41#include "cpu/thread_context.hh" | 37#include "arch/sparc/types.hh" 38#include "base/bitfield.hh" 39#include "base/trace.hh" 40#include "sim/full_system.hh" 41#include "cpu/base.hh" 42#include "cpu/thread_context.hh" |
42#if !FULL_SYSTEM 43#include "arch/sparc/process.hh" 44#endif | |
45#include "mem/page_table.hh" 46#include "sim/process.hh" 47#include "sim/full_system.hh" 48 49using namespace std; 50 51namespace SparcISA 52{ --- 608 unchanged lines hidden (view full) --- 661 p->M5_pid /*context id*/, false, entry.pte); 662 } 663 } 664} 665 666void 667SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 668{ | 43#include "mem/page_table.hh" 44#include "sim/process.hh" 45#include "sim/full_system.hh" 46 47using namespace std; 48 49namespace SparcISA 50{ --- 608 unchanged lines hidden (view full) --- 659 p->M5_pid /*context id*/, false, entry.pte); 660 } 661 } 662} 663 664void 665SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 666{ |
669#if !FULL_SYSTEM 670 doNormalFault(tc, trapType(), false); | 667 if (FullSystem) { 668 SparcFaultBase::invoke(tc, inst); 669 } else { 670 doNormalFault(tc, trapType(), false); |
671 | 671 |
672 Process *p = tc->getProcessPtr(); | 672 Process *p = tc->getProcessPtr(); |
673 | 673 |
674 //XXX This will only work in faults from a SparcLiveProcess 675 SparcLiveProcess *lp = dynamic_cast 676 assert(lp); | 674 //XXX This will only work in faults from a SparcLiveProcess 675 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 676 assert(lp); |
677 | 677 |
678 // Then adjust the PC and NPC 679 tc->pcState(lp->readSpillStart()); 680#else 681 SparcFaultBase::invoke(tc, inst); 682#endif | 678 // Then adjust the PC and NPC 679 tc->pcState(lp->readSpillStart()); 680 } |
683} 684 685void 686FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 687{ | 681} 682 683void 684FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst) 685{ |
688#if !FULL_SYSTEM 689 doNormalFault(tc, trapType(), false); | 686 if (FullSystem) { 687 SparcFaultBase::invoke(tc, inst); 688 } else { 689 doNormalFault(tc, trapType(), false); |
690 | 690 |
691 Process *p = tc->getProcessPtr(); | 691 Process *p = tc->getProcessPtr(); |
692 | 692 |
693 //XXX This will only work in faults from a SparcLiveProcess 694 SparcLiveProcess *lp = dynamic_cast 695 assert(lp); | 693 //XXX This will only work in faults from a SparcLiveProcess 694 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 695 assert(lp); |
696 | 696 |
697 // Then adjust the PC and NPC 698 tc->pcState(lp->readFillStart()); 699#else 700 SparcFaultBase::invoke(tc, inst); 701#endif | 697 // Then adjust the PC and NPC 698 tc->pcState(lp->readFillStart()); 699 } |
702} 703 704void 705TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 706{ | 700} 701 702void 703TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) 704{ |
707#if !FULL_SYSTEM 708 // In SE, this mechanism is how the process requests a service from the 709 // operating system. We'll get the process object from the thread context 710 // and let it service the request. | 705 if (FullSystem) { 706 SparcFaultBase::invoke(tc, inst); 707 } else { 708 // In SE, this mechanism is how the process requests a service from 709 // the operating system. We'll get the process object from the thread 710 // context and let it service the request. |
711 | 711 |
712 Process *p = tc->getProcessPtr(); | 712 Process *p = tc->getProcessPtr(); |
713 | 713 |
714 SparcLiveProcess *lp = dynamic_cast 715 assert(lp); | 714 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p); 715 assert(lp); |
716 | 716 |
717 lp->handleTrap(_n, tc); | 717 lp->handleTrap(_n, tc); |
718 | 718 |
719 // We need to explicitly advance the pc, since that's not done for us 720 // on a faulting instruction 721 PCState pc = tc->pcState(); 722 pc.advance(); 723 tc->pcState(pc); 724#else 725 SparcFaultBase::invoke(tc, inst); 726#endif | 719 // We need to explicitly advance the pc, since that's not done for us 720 // on a faulting instruction 721 PCState pc = tc->pcState(); 722 pc.advance(); 723 tc->pcState(pc); 724 } |
727} 728 729} // namespace SparcISA 730 | 725} 726 727} // namespace SparcISA 728 |