1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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302 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
303 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
304 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
305 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
306 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
307 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
308 MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
309 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
310 MiscReg PC = tc->readPC();
311 MiscReg NPC = tc->readNextPC();
312
313 TL++;
314
315 if (bits(PSTATE, 3,3)) {
316 PC &= mask(32);
317 NPC &= mask(32);
318 }
319
320 //set TSTATE.gl to gl
321 replaceBits(TSTATE, 42, 40, GL);
322 //set TSTATE.ccr to ccr
323 replaceBits(TSTATE, 39, 32, CCR);
324 //set TSTATE.asi to asi
325 replaceBits(TSTATE, 31, 24, ASI);
326 //set TSTATE.pstate to pstate
327 replaceBits(TSTATE, 20, 8, PSTATE);
328 //set TSTATE.cwp to cwp
329 replaceBits(TSTATE, 4, 0, CWP);
330
331 //Write back TSTATE
332 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
333
334 //set TPC to PC
335 tc->setMiscRegNoEffect(MISCREG_TPC, PC);
336 //set TNPC to NPC
337 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
338
339 //set HTSTATE.hpstate to hpstate
340 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
341
342 //TT = trap type;
343 tc->setMiscRegNoEffect(MISCREG_TT, tt);
344
345 //Update GL

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389 MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
390 //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
391 MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
392 MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
393 MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
394 //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
395 MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
396 MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
397 MiscReg PC = tc->readPC();
398 MiscReg NPC = tc->readNextPC();
399
400 if (bits(PSTATE, 3,3)) {
401 PC &= mask(32);
402 NPC &= mask(32);
403 }
404
405 //Increment the trap level
406 TL++;
407 tc->setMiscRegNoEffect(MISCREG_TL, TL);
408
409 //Save off state
410
411 //set TSTATE.gl to gl
412 replaceBits(TSTATE, 42, 40, GL);
413 //set TSTATE.ccr to ccr
414 replaceBits(TSTATE, 39, 32, CCR);
415 //set TSTATE.asi to asi
416 replaceBits(TSTATE, 31, 24, ASI);
417 //set TSTATE.pstate to pstate
418 replaceBits(TSTATE, 20, 8, PSTATE);
419 //set TSTATE.cwp to cwp
420 replaceBits(TSTATE, 4, 0, CWP);
421
422 //Write back TSTATE
423 tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
424
425 //set TPC to PC
426 tc->setMiscRegNoEffect(MISCREG_TPC, PC);
427 //set TNPC to NPC
428 tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
429
430 //set HTSTATE.hpstate to hpstate
431 tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
432
433 //TT = trap type;
434 tc->setMiscRegNoEffect(MISCREG_TT, tt);
435
436 //Update the global register level

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474
475 if (changedCWP)
476 {
477 CWP = (CWP + NWindows) % NWindows;
478 tc->setMiscReg(MISCREG_CWP, CWP);
479 }
480}
481
482void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
483{
484 //XXX The following constant might belong in a header file.
485 const Addr RSTVAddr = 0xFFF0000000ULL;
486 PC = RSTVAddr | ((TT << 5) & 0xFF);
487 NPC = PC + sizeof(MachInst);
488}
489
490void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)

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549 (level == Privileged && trapType() >= 384)) {
550 doNormalFault(tc, trapType(), true);
551 getHyperVector(tc, PC, NPC, trapType());
552 } else {
553 doNormalFault(tc, trapType(), false);
554 getPrivVector(tc, PC, NPC, trapType(), tl+1);
555 }
556
557 tc->setPC(PC);
558 tc->setNextPC(NPC);
559 tc->setNextNPC(NPC + sizeof(MachInst));
560}
561
562void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
563{
564 //For SPARC, when a system is first started, there is a power
565 //on reset Trap which sets the processor into the following state.
566 //Bits that aren't set aren't defined on startup.
567

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588 tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
589
590 //Enter RED state. We do this last so that the actual state preserved in
591 //the trap stack is the state from before this fault.
592 enterREDState(tc);
593
594 Addr PC, NPC;
595 getREDVector(trapType(), PC, NPC);
596 tc->setPC(PC);
597 tc->setNextPC(NPC);
598 tc->setNextNPC(NPC + sizeof(MachInst));
599
600 //These registers are specified as "undefined" after a POR, and they
601 //should have reasonable values after the miscregfile is reset
602 /*
603 // Clear all the soft interrupt bits
604 softint = 0;
605 // disable timer compare interrupts, reset tick_cmpr
606 tc->setMiscRegNoEffect(MISCREG_
607 tick_cmprFields.int_dis = 1;

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659
660 Process *p = tc->getProcessPtr();
661
662 //XXX This will only work in faults from a SparcLiveProcess
663 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
664 assert(lp);
665
666 //Then adjust the PC and NPC
667 Addr spillStart = lp->readSpillStart();
668 tc->setPC(spillStart);
669 tc->setNextPC(spillStart + sizeof(MachInst));
670 tc->setNextNPC(spillStart + 2*sizeof(MachInst));
671}
672
673void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
674{
675 doNormalFault(tc, trapType(), false);
676
677 Process * p = tc->getProcessPtr();
678
679 //XXX This will only work in faults from a SparcLiveProcess
680 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
681 assert(lp);
682
683 //Then adjust the PC and NPC
684 Addr fillStart = lp->readFillStart();
685 tc->setPC(fillStart);
686 tc->setNextPC(fillStart + sizeof(MachInst));
687 tc->setNextNPC(fillStart + 2*sizeof(MachInst));
688}
689
690void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
691{
692 //In SE, this mechanism is how the process requests a service from the
693 //operating system. We'll get the process object from the thread context
694 //and let it service the request.
695
696 Process *p = tc->getProcessPtr();
697
698 SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
699 assert(lp);
700
701 lp->handleTrap(_n, tc);
702
703 //We need to explicitly advance the pc, since that's not done for us
704 //on a faulting instruction
705 tc->setPC(tc->readNextPC());
706 tc->setNextPC(tc->readNextNPC());
707 tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
708}
709
710#endif
711
712} // namespace SparcISA
713