1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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279 //@todo Disable the mmu?
280 //@todo Disable watchpoints?
281 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
282 //HPSTATE.red = 1
283 HPSTATE |= (1 << 5);
284 //HPSTATE.hpriv = 1
285 HPSTATE |= (1 << 2);
286 tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
287}
288
289/**
290 * This sets everything up for a RED state trap except for actually jumping to
291 * the handler.
292 */
293
294void doREDFault(ThreadContext *tc, TrapType tt)

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335 //Update GL
336 tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
337
338 //set PSTATE.mm to 00
339 //set PSTATE.pef to 1
340 PSTATE |= (1 << 4);
341 //set PSTATE.am to 0
342 PSTATE &= ~(1 << 3);
343 //set PSTATE.priv to 0
344 PSTATE &= ~(1 << 2);
345 //set PSTATE.ie to 0
346 PSTATE &= ~(1 << 1);
347 //set PSTATE.cle to 0
348 PSTATE &= ~(1 << 9);
349 //PSTATE.tle is unchanged
350 //XXX Where is the tct bit?
351 //set PSTATE.tct to 0
352 tc->setMiscReg(MISCREG_PSTATE, PSTATE);
353
354 //set HPSTATE.red to 1

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446 //PSTATE.priv = 1
447 PSTATE |= (1 << 2);
448 //PSTATE.cle = PSTATE.tle
449 replaceBits(PSTATE, 9, 9, PSTATE >> 8);
450 }
451 else
452 {
453 //PSTATE.priv = 0
454 PSTATE &= ~(1 << 2);
455 //PSTATE.cle = 0
456 PSTATE &= ~(1 << 9);
457 }
458 //PSTATE.ie = 0
459 PSTATE &= ~(1 << 1);
460 //PSTATE.tle is unchanged
461 //PSTATE.tct = 0
462 //XXX Where exactly is this field?

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528 MiscReg TL = tc->readMiscReg(MISCREG_TL);
529 MiscReg TT = tc->readMiscReg(MISCREG_TT);
530 MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
531 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
532
533 Addr PC, NPC;
534
535 PrivilegeLevel current;
536 if(!(PSTATE & (1 << 2)))
537 current = User;
538 else if(!(HPSTATE & (1 << 2)))
539 current = Privileged;
540 else
541 current = Hyperprivileged;
542
543 PrivilegeLevel level = getNextLevel(current);
544
545 if(HPSTATE & (1 << 5) || TL == MaxTL - 1)
546 {
547 getREDVector(5, PC, NPC);
548 enterREDState(tc);
549 doREDFault(tc, TT);
550 }
551 else if(TL == MaxTL)
552 {
553 //Do error_state somehow?
554 //Probably inject a WDR fault using the interrupt mechanism.
555 //What should the PC and NPC be set to?
556 }
557 else if(TL > MaxPTL && level == Privileged)

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573
574 tc->setPC(PC);
575 tc->setNextPC(NPC);
576 tc->setNextNPC(NPC + sizeof(MachInst));
577}
578
579void PowerOnReset::invoke(ThreadContext * tc)
580{
581 //First, enter RED state.
582 enterREDState(tc);
583
584 //For SPARC, when a system is first started, there is a power
585 //on reset Trap which sets the processor into the following state.
586 //Bits that aren't set aren't defined on startup.
587
588 tc->setMiscReg(MISCREG_TL, MaxTL);
589 tc->setMiscReg(MISCREG_TT, trapType());
590 tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
591
592 //Turn on pef, set everything else to 0
593 tc->setMiscReg(MISCREG_PSTATE, 1 << 4);
594
595 //Turn on red and hpriv, set everything else to 0
596 MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
597 //HPSTATE.red = 1
598 HPSTATE |= (1 << 5);
599 //HPSTATE.hpriv = 1
600 HPSTATE |= (1 << 2);
601 //HPSTATE.ibe = 0
602 HPSTATE &= ~(1 << 10);
603 //HPSTATE.tlz = 0
604 HPSTATE &= ~(1 << 0);
605 tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
606
607 //The tick register is unreadable by nonprivileged software
608 tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
609
610 Addr PC, NPC;
611 getREDVector(trapType(), PC, NPC);
612 tc->setPC(PC);
613 tc->setNextPC(NPC);
614 tc->setNextNPC(NPC + sizeof(MachInst));
615
616 //These registers are specified as "undefined" after a POR, and they
617 //should have reasonable values after the miscregfile is reset

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