asi.cc (3804:fa7a01dddc7a) asi.cc (3823:1c8f87aa103e)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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99 (asi == ASI_FL8_SL) ||
100 (asi == ASI_FL16_SL) ||
101 (asi == ASI_LDTX_S) ||
102 (asi == ASI_LDTX_SL) ||
103 (asi == ASI_BLK_S) ||
104 (asi == ASI_BLK_SL);
105 }
106
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 90 unchanged lines hidden (view full) ---

99 (asi == ASI_FL8_SL) ||
100 (asi == ASI_FL16_SL) ||
101 (asi == ASI_LDTX_S) ||
102 (asi == ASI_LDTX_SL) ||
103 (asi == ASI_BLK_S) ||
104 (asi == ASI_BLK_SL);
105 }
106
107 bool AsiNucleus(ASI asi)
107 bool AsiIsNucleus(ASI asi)
108 {
109 return
110 (asi == ASI_N) ||
111 (asi == ASI_NL) ||
112 (asi == ASI_LDTX_N) ||
113 (asi == ASI_LDTX_NL);
114 }
115

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254 bool AsiIsQueue(ASI asi)
255 {
256 return asi == ASI_QUEUE;
257 }
258
259 bool AsiIsMmu(ASI asi)
260 {
261 return asi == ASI_MMU ||
108 {
109 return
110 (asi == ASI_N) ||
111 (asi == ASI_NL) ||
112 (asi == ASI_LDTX_N) ||
113 (asi == ASI_LDTX_NL);
114 }
115

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254 bool AsiIsQueue(ASI asi)
255 {
256 return asi == ASI_QUEUE;
257 }
258
259 bool AsiIsMmu(ASI asi)
260 {
261 return asi == ASI_MMU ||
262 asi == ASI_LSU_CONTROL_REG ||
262 (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 &&
263 asi <= ASI_IMMU_CTXT_ZERO_CONFIG) ||
264 (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 &&
265 asi <= ASI_IMMU_CTXT_NONZERO_CONFIG) ||
266 (asi >= ASI_IMMU &&
267 asi <= ASI_IMMU_TSB_PS1_PTR_REG) ||
268 (asi >= ASI_ITLB_DATA_IN_REG &&
269 asi <= ASI_TLB_INVALIDATE_ALL);

--- 24 unchanged lines hidden --- 		263 (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 &&
264 asi <= ASI_IMMU_CTXT_ZERO_CONFIG) ||
265 (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 &&
266 asi <= ASI_IMMU_CTXT_NONZERO_CONFIG) ||
267 (asi >= ASI_IMMU &&
268 asi <= ASI_IMMU_TSB_PS1_PTR_REG) ||
269 (asi >= ASI_ITLB_DATA_IN_REG &&
270 asi <= ASI_TLB_INVALIDATE_ALL);

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