utility.hh (12136:1070125670e2) utility.hh (12808:f275fd1244ce)
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
4 * Copyright (c) 2018 TU Dresden
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Andreas Hansson
42 * Sven Karlsson
43 * Alec Roelke
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated

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37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 * Sven Karlsson
44 * Alec Roelke
45 * Robert Scheffel
44 */
45
46#ifndef __ARCH_RISCV_UTILITY_HH__
47#define __ARCH_RISCV_UTILITY_HH__
48
49#include <cmath>
50#include <cstdint>
51#include <sstream>

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112inline uint64_t
113getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
114{
115 return 0;
116}
117
118inline void startupCPU(ThreadContext *tc, int cpuId)
119{
46 */
47
48#ifndef __ARCH_RISCV_UTILITY_HH__
49#define __ARCH_RISCV_UTILITY_HH__
50
51#include <cmath>
52#include <cstdint>
53#include <sstream>

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114inline uint64_t
115getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
116{
117 return 0;
118}
119
120inline void startupCPU(ThreadContext *tc, int cpuId)
121{
122 tc->activate();
120}
121
122inline void
123copyRegs(ThreadContext *src, ThreadContext *dest)
124{
125 // First loop through the integer registers.
126 for (int i = 0; i < NumIntRegs; ++i)
127 dest->setIntReg(i, src->readIntReg(i));

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178}
179
180inline uint64_t
181getExecutingAsid(ThreadContext *tc)
182{
183 return 0;
184}
185
123}
124
125inline void
126copyRegs(ThreadContext *src, ThreadContext *dest)
127{
128 // First loop through the integer registers.
129 for (int i = 0; i < NumIntRegs; ++i)
130 dest->setIntReg(i, src->readIntReg(i));

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181}
182
183inline uint64_t
184getExecutingAsid(ThreadContext *tc)
185{
186 return 0;
187}
188
186inline void
187initCPU(ThreadContext *, int cpuId)
188{
189 panic("initCPU not implemented for Riscv.\n");
190}
189/**
190 * init Cpu function
191 */
192void initCPU(ThreadContext *tc, int cpuId);
191
192} // namespace RiscvISA
193
194#endif // __ARCH_RISCV_UTILITY_HH__
193
194} // namespace RiscvISA
195
196#endif // __ARCH_RISCV_UTILITY_HH__