1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014-2015 Sven Karlsson
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| 4 * Copyright (c) 2018 TU Dresden |
5 * All rights reserved
6 *
7 * The license below extends only to copyright in the software and shall
8 * not be construed as granting a license to any other intellectual
9 * property including but not limited to intellectual property relating
10 * to a hardware implementation of the functionality of the software
11 * licensed hereunder. You may use the software subject to the license
12 * terms below provided that you ensure that this notice is replicated
13 * unmodified and in its entirety in all distributions of the software,
14 * modified or unmodified, in source code or in binary form.
15 *
16 * Copyright (c) 2016-2017 The University of Virginia
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Andreas Hansson
43 * Sven Karlsson
44 * Alec Roelke
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| 45 * Robert Scheffel |
46 */
47
48#ifndef __ARCH_RISCV_UTILITY_HH__
49#define __ARCH_RISCV_UTILITY_HH__
50
51#include <cmath>
52#include <cstdint>
53#include <sstream>
54#include <string>
55
56#include "arch/riscv/registers.hh"
57#include "base/types.hh"
58#include "cpu/reg_class.hh"
59#include "cpu/static_inst.hh"
60#include "cpu/thread_context.hh"
61
62namespace RiscvISA
63{
64
65template<typename T> inline bool
66isquietnan(T val)
67{
68 return false;
69}
70
71template<> inline bool
72isquietnan<float>(float val)
73{
74 return std::isnan(val)
75 && (reinterpret_cast<uint32_t&>(val)&0x00400000);
76}
77
78template<> inline bool
79isquietnan<double>(double val)
80{
81 return std::isnan(val)
82 && (reinterpret_cast<uint64_t&>(val)&0x0008000000000000ULL);
83}
84
85template<typename T> inline bool
86issignalingnan(T val)
87{
88 return false;
89}
90
91template<> inline bool
92issignalingnan<float>(float val)
93{
94 return std::isnan(val)
95 && (reinterpret_cast<uint32_t&>(val)&0x00200000);
96}
97
98template<> inline bool
99issignalingnan<double>(double val)
100{
101 return std::isnan(val)
102 && (reinterpret_cast<uint64_t&>(val)&0x0004000000000000ULL);
103}
104
105inline PCState
106buildRetPC(const PCState &curPC, const PCState &callPC)
107{
108 PCState retPC = callPC;
109 retPC.advance();
110 retPC.pc(curPC.npc());
111 return retPC;
112}
113
114inline uint64_t
115getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
116{
117 return 0;
118}
119
120inline void startupCPU(ThreadContext *tc, int cpuId)
121{
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| 122 tc->activate(); |
123}
124
125inline void
126copyRegs(ThreadContext *src, ThreadContext *dest)
127{
128 // First loop through the integer registers.
129 for (int i = 0; i < NumIntRegs; ++i)
130 dest->setIntReg(i, src->readIntReg(i));
131
132 // Lastly copy PC/NPC
133 dest->pcState(src->pcState());
134}
135
136inline std::string
137registerName(RegId reg)
138{
139 if (reg.isIntReg()) {
140 if (reg.index() >= NumIntArchRegs) {
141 /*
142 * This should only happen if a instruction is being speculatively
143 * executed along a not-taken branch, and if that instruction's
144 * width was incorrectly predecoded (i.e., it was predecoded as a
145 * full instruction rather than a compressed one or vice versa).
146 * It also should only happen if a debug flag is on that prints
147 * disassembly information, so rather than panic the incorrect
148 * value is printed for debugging help.
149 */
150 std::stringstream str;
151 str << "?? (x" << reg.index() << ')';
152 return str.str();
153 }
154 return IntRegNames[reg.index()];
155 } else {
156 if (reg.index() >= NumFloatRegs) {
157 std::stringstream str;
158 str << "?? (f" << reg.index() << ')';
159 return str.str();
160 }
161 return FloatRegNames[reg.index()];
162 }
163}
164
165inline void
166skipFunction(ThreadContext *tc)
167{
168 panic("Not Implemented for Riscv");
169}
170
171inline void
172advancePC(PCState &pc, const StaticInstPtr &inst)
173{
174 inst->advancePC(pc);
175}
176
177static inline bool
178inUserMode(ThreadContext *tc)
179{
180 return true;
181}
182
183inline uint64_t
184getExecutingAsid(ThreadContext *tc)
185{
186 return 0;
187}
188
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186inline void
187initCPU(ThreadContext *, int cpuId)
188{
189 panic("initCPU not implemented for Riscv.\n");
190}
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189/**
190 * init Cpu function
191 */
192void initCPU(ThreadContext *tc, int cpuId); |
193
194} // namespace RiscvISA
195
196#endif // __ARCH_RISCV_UTILITY_HH__
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