| 1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014-2015 Sven Karlsson |
| 4 * Copyright (c) 2018 TU Dresden |
| 5 * All rights reserved 6 * 7 * The license below extends only to copyright in the software and shall 8 * not be construed as granting a license to any other intellectual 9 * property including but not limited to intellectual property relating 10 * to a hardware implementation of the functionality of the software 11 * licensed hereunder. You may use the software subject to the license 12 * terms below provided that you ensure that this notice is replicated --- 24 unchanged lines hidden (view full) --- 37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Authors: Andreas Hansson 43 * Sven Karlsson 44 * Alec Roelke |
| 45 * Robert Scheffel |
| 46 */ 47 48#ifndef __ARCH_RISCV_UTILITY_HH__ 49#define __ARCH_RISCV_UTILITY_HH__ 50 51#include <cmath> 52#include <cstdint> 53#include <sstream> --- 60 unchanged lines hidden (view full) --- 114inline uint64_t 115getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 116{ 117 return 0; 118} 119 120inline void startupCPU(ThreadContext *tc, int cpuId) 121{ |
| 122 tc->activate(); |
| 123} 124 125inline void 126copyRegs(ThreadContext *src, ThreadContext *dest) 127{ 128 // First loop through the integer registers. 129 for (int i = 0; i < NumIntRegs; ++i) 130 dest->setIntReg(i, src->readIntReg(i)); --- 50 unchanged lines hidden (view full) --- 181} 182 183inline uint64_t 184getExecutingAsid(ThreadContext *tc) 185{ 186 return 0; 187} 188 |
| 189/** 190 * init Cpu function 191 */ 192void initCPU(ThreadContext *tc, int cpuId); |
| 193 194} // namespace RiscvISA 195 196#endif // __ARCH_RISCV_UTILITY_HH__ |