types.hh (11723:0596db108c53) | types.hh (11726:11950d45640b) |
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1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * | 1/* 2 * Copyright (c) 2013 ARM Limited 3 * Copyright (c) 2014 Sven Karlsson 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * |
15 * Copyright (c) 2016 The University of Virginia 16 * All rights reserved. 17 * |
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15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its --- 9 unchanged lines hidden (view full) --- 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Andreas Hansson 39 * Sven Karlsson | 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its --- 9 unchanged lines hidden (view full) --- 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Andreas Hansson 42 * Sven Karlsson |
43 * Alec Roelke |
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40 */ 41 42#ifndef __ARCH_RISCV_TYPES_HH__ 43#define __ARCH_RISCV_TYPES_HH__ 44 45#include "arch/generic/types.hh" 46 47namespace RiscvISA 48{ 49typedef uint32_t MachInst; 50typedef uint64_t ExtMachInst; 51 | 44 */ 45 46#ifndef __ARCH_RISCV_TYPES_HH__ 47#define __ARCH_RISCV_TYPES_HH__ 48 49#include "arch/generic/types.hh" 50 51namespace RiscvISA 52{ 53typedef uint32_t MachInst; 54typedef uint64_t ExtMachInst; 55 |
52typedef GenericISA::SimplePCState<MachInst> PCState; | 56typedef GenericISA::UPCState<MachInst> PCState; |
53} 54 55 56#endif // __ARCH_RISCV_TYPES_HH__ | 57} 58 59 60#endif // __ARCH_RISCV_TYPES_HH__ |