1/*
2 * Copyright (c) 2013 ARM Limited
3 * Copyright (c) 2014 Sven Karlsson
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2016 The University of Virginia
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the

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45
46#ifndef __ARCH_RISCV_TYPES_HH__
47#define __ARCH_RISCV_TYPES_HH__
48
49#include "arch/generic/types.hh"
50
51namespace RiscvISA
52{
53typedef uint32_t MachInst;
54typedef uint64_t ExtMachInst;
55
56typedef GenericISA::UPCState<MachInst> PCState;
57}
58
59
60#endif // __ARCH_RISCV_TYPES_HH__