1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 289 unchanged lines hidden (view full) --- 298} 299 300Fault 301TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) 302{ 303 if (FullSystem) 304 panic("translateData not implemented in RISC-V.\n"); 305 |
306 // In the O3 CPU model, sometimes a memory access will be speculatively 307 // executed along a branch that will end up not being taken where the 308 // address is invalid. In that case, return a fault rather than trying 309 // to translate it (which will cause a panic). Since RISC-V allows 310 // unaligned memory accesses, this should only happen if the request's 311 // length is long enough to wrap around from the end of the memory to the 312 // start. 313 assert(req->getSize() > 0); 314 if (req->getVaddr() + req->getSize() - 1 < req->getVaddr()) 315 return make_shared<GenericPageTableFault>(req->getVaddr()); 316 |
317 Process * p = tc->getProcessPtr(); 318 319 Fault fault = p->pTable->translate(req); 320 if (fault != NoFault) 321 return fault; 322 323 return NoFault; 324} --- 48 unchanged lines hidden --- |